DROM and IROM mapping in the bootloader

[kolban]

I'm down in the weeds of the bootloader trying to get a comprehension (I'm finding it hard and if others have walked this path before, please make yourself known).

As I study this code:

https://github.com/espressif/esp-idf/bl ... art.c#L613

I find myself puzzled. Here is why.

Looking at the code, if I am understanding it correctly, it is mapping flash storage into the ESP32 address space via MMU. If we look at the code, we see that it has diagnostics capabilities to log information to the console. If we enable those diagnostics we see the following:

Code: Select all

D (527) boot: configure drom and irom and start
V (532) boot: d mmu set paddr=00020000 vaddr=400d0000 size=70724 n=2
V (538) boot: rc=0
V (540) boot: rc=0
V (542) boot: i mmu set paddr=00010000 vaddr=3f400000 size=15780 n=1
V (548) boot: rc=0
V (551) boot: rc=0

The way I am interpreting this is that storage at flash offset 0x2 0000 is being mapped into the address space at 0x400D 0000 while storage at flash offset 0x1 0000 is being mapped into the address space at 0x3F40 0000.

My belief is that these are read only data (its flash) that correspond to constant data and binary instructions.

My problem is that if I read these correctly and "d" means data and "i" means instruction, then if I contrast these with the technical reference manual which contains:

Addresses below 0x4000_0000 are serviced using the data bus. Addresses in the range 0x4000_0000 ~ 0x4FFF_FFFF are serviced using the instruction bus.

... they seem backwards. I would have imagined instructions being loaded above 0x4000 0000 and data being loaded before 0x4000 0000 and not as shown in the diagnostics and code.

[WiFive]

Seems like a switcheroo in this code
https://github.com/espressif/esp-idf/bl ... #L558-L579