Inconsistencies with RTC_CNTL_GLITCH_RST_EN Default Setting in ESP32-C3 Technical Reference Manual

[mnorouzi72]

Hello everyone,

I am using an ESP32-C3 and have encountered some inconsistencies related to the RTC_CNTL_GLITCH_RST_EN bit in the RTC_CNTL_ANA_CONF_REG register. According to the ESP32-C3 Technical Reference Manual, it is stated:

> "Once detecting a glitch on XTAL_CLK that affects the circuit’s normal operation, the Clock Glitch Detection module triggers a system reset if RTC_CNTL_GLITCH_RST_EN bit is enabled. By default, this bit is set to enable a reset."

However, when I examine the picture of the RTC_CNTL_ANA_CONF_REG in the reference manual, it appears that RTC_CNTL_GLITCH_RST_EN is not set by default.

My questions are:

1. Why does the picture of RTC_CNTL_ANA_CONF_REG show RTC_CNTL_GLITCH_RST_EN as not set, despite the statement that it is enabled by default?

According to the technical reference manual, this bit should be set by default to enable a reset. This discrepancy is confusing, and I would like to understand the correct default state of this bit.

2. Why is the actual value of RTC_CNTL_GLITCH_RST_EN zero when read, contrary to the manual's statement that it is enabled by default?

I have read the RTC_CNTL_ANA_CONF_REG register, and the RTC_CNTL_GLITCH_RST_EN bit is indeed zero. This seems to contradict the documentation. Could there be an error in the manual, or is there something I am missing?

3. Why do I get a reset reason of `RESET_REASON_SYS_CLK_GLITCH` when the value of RTC_CNTL_GLITCH_RST_EN is zero?

I used the esp_rom_get_reset_reason function to find the reset reason of the CPU, and it returned RESET_REASON_SYS_CLK_GLITCH. How can this be if the RTC_CNTL_GLITCH_RST_EN bit is not set? What other mechanisms could be causing this system reset?

Any insights or clarifications on these issues would be greatly appreciated. Thank you!