- Guru Meditation Error: Core 0 panic'ed (Interrupt wdt timeout on CPU0).
- Core 0 register dump:
- PC : 0x401b207e PS : 0x00060e34 A0 : 0x800d2bc6 A1 : 0x3ffc6240
- 0x401b207e: esp_pm_impl_waiti at /home/wxd/esp/esp-idf/components/esp_pm/pm_impl.c:839
- A2 : 0x3ffbe910 A3 : 0x00060e20 A4 : 0x80090320 A5 : 0x3ffc2ec0
- A6 : 0x00000003 A7 : 0x00060023 A8 : 0x80127025 A9 : 0x3ffc6230
- A10 : 0x00000003 A11 : 0x00060e23 A12 : 0x00060e20 A13 : 0x3ffb0b40
- A14 : 0x3ffb13d0 A15 : 0x3ffb13d0 SAR : 0x0000001d EXCCAUSE: 0x00000005
- EXCVADDR: 0x00000000 LBEG : 0x00000000 LEND : 0x00000000 LCOUNT : 0x00000000
- Backtrace:0x401b207b:0x3ffc62400x400d2bc3:0x3ffc6260 0x4008e14c:0x3ffc6280
- 0x401b207b: cpu_ll_waiti at /home/wxd/esp/esp-idf/components/hal/esp32/include/hal/cpu_ll.h:183
- (inlined by) esp_pm_impl_waiti at /home/wxd/esp/esp-idf/components/esp_pm/pm_impl.c:837
- 0x400d2bc3: esp_vApplicationIdleHook at /home/wxd/esp/esp-idf/components/esp_system/freertos_hooks.c:63
- 0x4008e14c: prvIdleTask at /home/wxd/esp/esp-idf/components/freertos/tasks.c:3974
chip: esp32-U4WDH
IDF version:v4.4 with commit 8153bfe412
platform: vscode on linux
description:
Need low latency gpio interrupt, so wrote the following code in assembly to test the feasibility. ETS_GPIO_INTR_SOURCE is linked to number 31 of the interrupt matrix using intr_matrix_set(). The triggering mode is GPIO_INTR_NEGEDGE. The isr is on level5 using xt_highint5. The isr simply toggles gpio13 once.
Bluetooth has been disabled and CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL is set to 4.
problem:
The isr is triggered by desired condition and voltage toggle is observed using oscilloscope, but program crashes due to interrupt wdt timeout on core0. The followings are backtrace infos and detailed coredump is in the attachment:
- #include <xtensa/coreasm.h>
- #include <xtensa/corebits.h>
- #include <xtensa/config/system.h>
- #include "freertos/xtensa_context.h"
- #include "esp_private/panic_reason.h"
- #include "sdkconfig.h"
- #include "soc/soc.h"
- #include "soc/gpio_reg.h"
- #include "soc/dport_reg.h"
- #define L5_INTR_STACK_SIZE 12
- #define LX_INTR_A15_OFFSET 0
- #define LX_INTR_A14_OFFSET 4
- #define LX_INTR_A13_OFFSET 8
- #define STB_PIN 4
- #define LOAD_PIN 0 // 32 - 32
- #define CLK_PIN 1 // 33 - 32
- #define BIT_PIN 4 // 36 - 32
- #define BSY_PIN 13
- #define BUF_SIZE 20480
- .data
- _l5_intr_stack:
- .space L5_INTR_STACK_SIZE
- .section .iram1,"ax"
- .global xt_highint5
- .type xt_highint5,@function
- .align 4
- xt_highint5:
- movi a0, _l5_intr_stack // assuming a0 saved restored by EXCSAVE_5 at the end of this
- s32i a15, a0, LX_INTR_A15_OFFSET
- s32i a14, a0, LX_INTR_A14_OFFSET
- s32i a13, a0, LX_INTR_A13_OFFSET
- /* Clear interupt on STB_PIN which gpio4 in current hardware design */
- movi a14, GPIO_STATUS_W1TC_REG
- movi a15, (1 << STB_PIN)
- s32i a15, a14, 0
- memw
- // set busy high
- movi a12, GPIO_OUT_W1TS_REG
- movi a13, GPIO_OUT_W1TC_REG
- movi a15, (1 << BSY_PIN)
- s32i a15, a12, 0
- s32i a15, a13, 0
- l32i a15, a0, LX_INTR_A15_OFFSET
- l32i a14, a0, LX_INTR_A14_OFFSET
- l32i a13, a0, LX_INTR_A13_OFFSET
- rsr a0, EXCSAVE_5 // restore a0
- rfi 5
- .global ld_include_xt_highint5
- ld_include_xt_highint5:
Digging into the backtrace, it shows that "waiti 0" command somehow causes the problem.
Any hint on the reason and possible fixes?
Thanks & Regards
wxd