RTC memory synchronization (RISCV-ULP vs. CPU)

[DrMickeyLauer]

In my application the RISCV-ULP is responsible for blinking LEDs on behalf of the CPU. To indicate which LEDs have to blink we use a shared state variable that gets written by the CPU and read/reset by the RISCV-ULP.

Since the lock synchronization may introduce unwanted latencies, I wonder about the worst case if we don't do it. What can happen if read/write or two writes collide? Will either one win, will the resulting value be completely random or will the system crash?

[liaifat85]

I think you are experiencing race condition: viewtopic.php?t=6771

[MicroController]

will the resulting value be completely random or will the system crash?

I would be shocked if the hardware would fail to synchronize any memory accesses in this manner.