Capabilities of the ESP memory systems

[daniSi]

Hi,

I have read already a lot about the different RAM memory usage possibilities but somehow it doesn't match what I have read with the program I am testing.

• I want to put data into IRAM location with use of

  Code: Select all

  uint8_t* test = heap_caps_malloc(12, MALLOC_CAP_32BIT);

  Because the data is uint8_t I would expect I can write to the buffer only on indexes 0, 3, 7, ... But regardless to this I can normaly store the data to any index. It looks like not the 32bit aligned memory is used but DRAM?

• I tried to get the left memory from different memory systems after allocating 40kB of memory from different systems. The values before allocation:
  MALLOC_CAP_IRAM_8BIT: 0 B
  MALLOC_CAP_32BIT: 388944 B
  MALLOC_CAP_DMA: 381132 B
  MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT: 388944 B
  MALLOC_CAP_DEFAULT: 388944 B
  MALLOC_CAP_RTCRAM: 7812 B
  MALLOC_CAP_EXEC|MALLOC_CAP_INTERNAL: 368016 B
  
  the result after allocation:
  MALLOC_CAP_IRAM_8BIT: 0 B - Difference: 0 B
  MALLOC_CAP_32BIT: 348940 B - Difference: 40004 B
  MALLOC_CAP_DMA: 341128 B - Difference: 40004 B
  MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT: 348940 B - Difference: 40004 B
  MALLOC_CAP_DEFAULT: 348940 B - Difference: 40004 B
  MALLOC_CAP_RTCRAM: 7812 B - Difference: 0 B
  MALLOC_CAP_EXEC|MALLOC_CAP_INTERNAL: 328012 B - Difference: 40004 B

Question: Why the value decreases on all memory systems (regardless if I use MALLOC_CAP_32BIT, MALLOC_CAP_DEFAULT, MALLOC_CAP_DMA)? Its like the IRAM and DRAM would be the same memory?

I am using the ESP32-S3

[MicroController]

Why the value decreases on all memory systems (regardless if I use MALLOC_CAP_32BIT, MALLOC_CAP_DEFAULT, MALLOC_CAP_DMA)?

That's because "capabilities" are not the same as "memory regions". A single memory region may have more than one capability, e.g. memory that is byte-addressable is naturally also word-addressable. When you say you want word-addressable memory, you will get memory that is at least word addressable.

Its like the IRAM and DRAM would be the same memory?

That's because it mostly is. Looking at the memory address mapping of the S3 (TRM v1.1, p. 388, table 4-1), you'll find that there is only 32kb of RAM (SRAM 0) which are exclusive to the I-bus, and the 416kb of SRAM 1 are both I-bus and D-bus accessible. So, most of the RAM can be used as IRAM or DRAM as desired.

[daniSi]

Thanks for the quick reply.

Still I have some question open which I just don't understand. For e.g.

After building a program the output is as followed:
Used static IRAM: 53686 bytes ( 308554 remain, 14.8% used)
.text size: 52659 bytes
.vectors size: 1027 bytes
Used stat D/IRAM: 13185 bytes ( 159743 remain, 7.6% used)
.data size: 10609 bytes
.bss size: 2576 bytes

To where now this number do match, because sum of the then static IRAM is 362240 B and stat D/IRAM 172928?

Maybe my questions are not in place but I just don't know how to interpret all these numbers.

[MicroController]

Don't care about those numbers. The only meaningful information here is that you'll have about 308+159kB of free RAM for allocations at runtime.