ESP32-S3 : Use of SPI in slave mode without CS line. Is it possible ?

[ThomasESP32]

Good morning,

I am working on a ESP32-S3 microcontroller and I need to implement the following feature.

I have an external component that generates a 4000Hz Clock and sends datas on the Rising Edge of the Clock on another
line (Let's say DATA line).
I need to latch the DATA bits on the rising edges of the Clock using the ESP32-S3 but I don't want to do this using interrupts
on the CLK signal because the period is 250us. Every 250us, I would have an interrupt in my program and because I
have a lot of processes to do, I fear this might disturb the processes.

I see that this is typically what SPI in slave mode can do (Except the fact that there is no CS line in our case).

Using the SPI Slave driver, I wanted to get the datas on the DATA line on the rising edges of the CLOCK.
However, because I have no CS line, it seems that the :
err = spi_slave_transmit(SPI2_HOST, &Transaction, portMAX_DELAY);
never exits.
The driver does not seem to understand that a transaction occur.

So my question is the following. Is it possible to use the SPI driver in Slave mode without the use of a CS line ?
If the answer is no, is it possible to use the SPI in Slave mode without the driver and without the CS line and how ?

Do you have another idea please ?

Thank you for your help on the subject,
Best regards,

Thomas TRUILHE

[a2800276]

However, because I have no CS line, it seems that the :
err = spi_slave_transmit(SPI2_HOST, &Transaction, portMAX_DELAY);
never exits.

That api seems to expect transactions delineated by C's changes.

Two options that come to mind:

- toggle the CS state on a fake pin by setting their pull-up and pull down configuration.
- check whether this is a limitation of the api or the chip peripheral. If it's the latter, use the peripheral without the IDF api

[MicroController]

Note that the CS signal is also needed for (re-)synchronization, so that the slave can know when a transaction and also a byte starts. Without CS, a slave would have no defined way to synchronize to the bytes sent if it were to ever miss a clock on the bus (e.g. if the master starts sending before the slave has initialized its SPI hardware.)

[ThomasESP32]

So, it seems mandatory to have the CS line set in SPI Slave Mode.
Am I right ?

Reading the Esp32-S3, it seems that it is included in the workflow.

Best regards,

Thomas TRUILHE

[ThomasESP32]

According to the reference manual, in the register : Register 30.9. SPI_MISC_REG (For SPI3 Only) (0x0020)
It seems that all the bits :
SPI_CS0_DIS SPI CS0 pin enable bit. 1: disable CS0. 0: SPI_CS0 signal is from/to CS0 pin.
SPI_CS1_DIS SPI CS1 pin enable bit. 1: disable CS1. 0: SPI_CS1 signal is from/to CS1 pin.
SPI_CS2_DIS SPI CS2 pin enable bit. 1: disable CS2. 0: SPI_CS2 signal is from/to CS2 pin.

Can be set to disable the CSX pins. But how can I be sure that the SPI3 will work or not in this case ?
Has someone already tried to use the SPI3 without CS line please ?

Best regards,

Thomas TRUILHE

[ThomasESP32]

Another question please, if I do not use the CS line.
Do you know if the SPI_WX_REG will be written when datas are received ?

I want to say, do I have the possibility to read these buffer manually ? Without the interruption trigger ?