ESP32-C3-MINI-1U reboot loop when switching GPIO7

Post Reply
innomkr
Posts: 7
Joined: Wed Sep 22, 2021 4:29 am

ESP32-C3-MINI-1U reboot loop when switching GPIO7

Postby innomkr » Wed Apr 06, 2022 2:38 pm

Hi guys... I am about to go crazy. I am working on a smart switch with 2 coil latching relay. I have made two prototypes - one with ESP32-C3-MINI-1U(with antenna connector) and one with ESP32-C3-MINI-1(PCB antenna).

My firmware is working absolutely fine on the ESP32-C3-MINI-1 but today I received the prototype with ESP32-C3-MINI-1U and as soon as I switch off the relay(output a 100ms impulse from GPIO7) my fw crashes.

After many hours of struggling I found out that the reboot happens when the gpio_set_level fucntion is called.

I wrote a very simple fw to eliminate any other failure options:

Code: Select all

#include <stdio.h>
#include <freertos/FreeRTOS.h>
#include <freertos/timers.h>
#include <sdkconfig.h>
#include "driver/gpio.h"
#include "freertos/task.h"

#define OUTPUT_GPIO_ON    6ULL
#define OUTPUT_GPIO_OFF   7ULL
#define LED               10ULL
void app_main(void)
{
    
    gpio_config_t io_conf = {
        .mode = GPIO_MODE_OUTPUT,
        .pull_down_en = 1,
    };

    uint64_t pin_mask = (((uint64_t)1 << OUTPUT_GPIO_ON ) | ((uint64_t)1 << OUTPUT_GPIO_OFF ) | ((uint64_t)1 << LED ));
    io_conf.pin_bit_mask = pin_mask;
    gpio_config(&io_conf);

    while (true)
    {
        
        gpio_set_level(OUTPUT_GPIO_ON, 1);
        gpio_set_level(LED, 1);
        vTaskDelay(200/portTICK_PERIOD_MS);
        printf("On-0\n");
        gpio_set_level(OUTPUT_GPIO_ON, 0);
        gpio_set_level(LED, 0);

        printf("Wait 3s\n");
        vTaskDelay(3000/portTICK_PERIOD_MS);

        printf("Off-1\n");
        gpio_set_level(OUTPUT_GPIO_OFF, 1);
        vTaskDelay(200/portTICK_PERIOD_MS);
        printf("Off-0\n");
        gpio_set_level(OUTPUT_GPIO_OFF, 0); 

        printf("Wait 3s\n");
        vTaskDelay(3000/portTICK_PERIOD_MS);    
    }
    
}
This is the serial output. No core dump is generated even though core dump to flash is enabled in SDK Config.

Code: Select all

�ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x1 (POWERON),boot:0xd (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fcd6100,len:0x1fc8
load:0x403ce000,len:0x994
load:0x403d0000,len:0x3244
SHA-256 comparison failed:
Calculated: 7151acbe2330d3bc0b105bd0c08fd1bf3a2b5354f014f6f1ddeed52c363eeade
Expected: 822b0184d99951694572e40758c955781494e601ed0bc04c27433a188557aaf4
Attempting to boot anyway...
entry 0x403ce000
I (48) boot: ESP-IDF v4.3.2-dirty 2nd stage bootloader
I (49) boot: compile time 17:22:37
D (49) bootloader_flash: XMC chip detected by RDID (00204016), skip.
D (53) bootloader_flash: mmu set block paddr=0x00000000 (was 0xffffffff)
I (60) boot: chip revision: 3
D (64) boot.esp32c3: magic e9
D (67) boot.esp32c3: segments 03
D (70) boot.esp32c3: spi_mode 02
D (74) boot.esp32c3: spi_speed 0f
D (77) boot.esp32c3: spi_size 02
I (80) boot.esp32c3: SPI Speed      : 80MHz
I (85) boot.esp32c3: SPI Mode       : DIO
I (90) boot.esp32c3: SPI Flash Size : 4MB
D (94) boot: Enabling RTCWDT(9000 ms)
I (98) boot: Enabling RNG early entropy source...
D (104) bootloader_flash: mmu set paddr=00000000 count=1 size=c00 src_addr=8000 src_addr_aligned=0
D (113) boot: mapped partition table 0x8000 at 0x3c008000
D (118) flash_parts: partition table verified, 4 entries
I (123) boot: Partition Table:
I (127) boot: ## Label            Usage          Type ST Offset   Length
D (135) boot: load partition table entry 0x3c008000
D (139) boot: type=1 subtype=2
I (143) boot:  0 nvs              WiFi data        01 02 00009000 00006000
D (150) boot: load partition table entry 0x3c008020
D (155) boot: type=1 subtype=1
I (158) boot:  1 phy_init         RF data          01 01 0000f000 00001000
D (166) boot: load partition table entry 0x3c008040
D (171) boot: type=0 subtype=0
I (174) boot:  2 factory          factory app      00 00 00010000 00100000
I (181) boot: End of partition table
D (186) boot: Trying partition index -1 offs 0x10000 size 0x100000
D (192) esp_image: reading image header @ 0x10000
D (197) bootloader_flash: mmu set block paddr=0x00010000 (was 0xffffffff)
D (204) esp_image: image header: 0xe9 0x06 0x02 0x01 403802ca
I (209) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=06b10h ( 27408) map
D (218) esp_image: free data page_count 0x0000003f
D (223) bootloader_flash: mmu set paddr=00010000 count=1 size=6b10 src_addr=10020 src_addr_aligned=10000
D (237) bootloader_flash: mmu set block paddr=0x00010000 (was 0xffffffff)
I (239) esp_image: segment 1: paddr=00016b38 vaddr=3fc8a600 size=02bc8h ( 11208) load
D (248) esp_image: free data page_count 0x0000003f
D (252) bootloader_flash: mmu set paddr=00010000 count=1 size=2bc8 src_addr=16b38 src_addr_aligned=10000
D (264) bootloader_flash: mmu set block paddr=0x00010000 (was 0xffffffff)
I (269) esp_image: segment 2: paddr=00019708 vaddr=40380000 size=06910h ( 26896) load
D (277) esp_image: free data page_count 0x0000003f
D (282) bootloader_flash: mmu set paddr=00010000 count=2 size=6910 src_addr=19708 src_addr_aligned=10000
D (297) bootloader_flash: mmu set block paddr=0x00020000 (was 0xffffffff)
I (299) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=13638h ( 79416) map
D (307) esp_image: free data page_count 0x0000003f
D (312) bootloader_flash: mmu set paddr=00020000 count=2 size=13638 src_addr=20020 src_addr_aligned=20000
D (334) bootloader_flash: mmu set block paddr=0x00030000 (was 0xffffffff)
I (335) esp_image: segment 4: paddr=00033660 vaddr=40386910 size=03b9ch ( 15260) load
D (339) esp_image: free data page_count 0x0000003f
D (343) bootloader_flash: mmu set paddr=00030000 count=1 size=3b9c src_addr=33660 src_addr_aligned=30000
D (356) bootloader_flash: mmu set block paddr=0x00030000 (was 0xffffffff)
I (360) esp_image: segment 5: paddr=00037204 vaddr=50000000 size=00010h (    16) load
D (368) esp_image: free data page_count 0x0000003f
D (373) bootloader_flash: mmu set paddr=00030000 count=1 size=10 src_addr=37204 src_addr_aligned=30000
D (383) bootloader_flash: mmu set block paddr=0x00030000 (was 0xffffffff)
D (389) boot: Calculated hash: 08dbe57907b75ad39409c54456e1b3aab72801716df30ddcf4acc316c059d512
I (402) boot: Loaded app from partition at offset 0x10000
I (404) boot: Disabling RNG early entropy source...
D (410) boot: Mapping segment 0 as DROM
D (414) boot: Mapping segment 3 as IROM
D (418) boot: calling set_cache_and_start_app
D (422) boot: configure drom and irom and start
D (427) boot: start: 0x403802ca
0x403802ca: call_start_cpu0 at /Users/miroslavpetrov/esp/esp-idf/components/esp_system/port/cpu_start.c:254

I (441) cpu_start: Pro cpu up.
D (441) efuse: In EFUSE_BLK2__DATA4_REG is used 3 bits starting with 0 bit
D (441) efuse: In EFUSE_BLK2__DATA4_REG is used 8 bits starting with 12 bit
D (448) efuse: In EFUSE_BLK1__DATA3_REG is used 3 bits starting with 18 bit
D (455) efuse: In EFUSE_BLK1__DATA5_REG is used 5 bits starting with 5 bit
D (462) efuse: In EFUSE_BLK1__DATA4_REG is used 7 bits starting with 7 bit
D (468) efuse: In EFUSE_BLK1__DATA4_REG is used 7 bits starting with 14 bit
D (476) efuse: In EFUSE_BLK1__DATA4_REG is used 8 bits starting with 21 bit
D (483) efuse: In EFUSE_BLK1__DATA4_REG is used 3 bits starting with 29 bit
D (490) efuse: In EFUSE_BLK1__DATA5_REG is used 5 bits starting with 0 bit
D (508) clk: RTC_SLOW_CLK calibration value: 3694605
I (514) cpu_start: Pro cpu start user code
I (514) cpu_start: cpu freq: 160000000
I (514) cpu_start: Application information:
I (516) cpu_start: Project name:     63a-test
I (521) cpu_start: App version:      1
I (526) cpu_start: Compile time:     Apr  6 2022 17:22:44
I (532) cpu_start: ELF file SHA256:  f43142a916388d69...
I (538) cpu_start: ESP-IDF:          v4.3.2-dirty
D (543) memory_layout: Checking 4 reserved memory ranges:
D (549) memory_layout: Reserved memory range 0x3fc80000 - 0x3fc8a600
D (555) memory_layout: Reserved memory range 0x3fc8a600 - 0x3fc8e3c0
D (562) memory_layout: Reserved memory range 0x3fcdf060 - 0x3fce0000
D (568) memory_layout: Reserved memory range 0x50000000 - 0x50000010
D (575) memory_layout: Building list of available memory regions:
D (581) memory_layout: Available memory region 0x3fc8e3c0 - 0x3fca0000
D (587) memory_layout: Available memory region 0x3fca0000 - 0x3fcc0000
D (594) memory_layout: Available memory region 0x3fcc0000 - 0x3fcdf060
D (600) memory_layout: Available memory region 0x50000010 - 0x50002000
I (607) heap_init: Initializing. RAM available for dynamic allocation:
D (614) heap_init: New heap initialised at 0x3fc8e3c0
I (619) heap_init: At 3FC8E3C0 len 00031C40 (199 KiB): DRAM
I (626) heap_init: At 3FCC0000 len 0001F060 (124 KiB): STACK/DRAM
D (632) heap_init: New heap initialised at 0x50000010
I (638) heap_init: At 50000010 len 00001FF0 (7 KiB): RTCRAM
D (644) FLASH_HAL: extra_dummy: 0
D (647) spi_flash: trying chip: issi
D (651) spi_flash: trying chip: gd
D (654) spi_flash: trying chip: mxic
D (658) spi_flash: trying chip: winbond
D (662) spi_flash: trying chip: boya
D (666) spi_flash: trying chip: generic
I (669) spi_flash: detected chip: generic
I (674) spi_flash: flash io: dio
D (678) cpu_start: calling init function: 0x4200002a
0x4200002a: esp_ota_init_app_elf_sha256 at /Users/miroslavpetrov/esp/esp-idf/components/app_update/esp_app_desc.c:76

D (683) intr_alloc: Connected src 39 to int 2 (cpu 0)
I (688) sleep: Configure to isolate all GPIO pins in sleep state
I (695) sleep: Enable automatic switching of GPIO sleep configuration
I (702) esp_core_dump_uart: Init core dump to UART
D (708) intr_alloc: Connected src 50 to int 3 (cpu 0)
I (713) cpu_start: Starting scheduler.
D (717) intr_alloc: Connected src 37 to int 4 (cpu 0)
D (717) heap_init: New heap initialised at 0x3fcc0000
D (717) intr_alloc: Connected src 33 to int 7 (cpu 0)
I (727) gpio: GPIO[6]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 1| Intr:0 
I (727) gpio: GPIO[7]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 1| Intr:0 
I (737) gpio: GPIO[10]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 1| Intr:0 
On-0
Wait 3s
---------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------CRASHES HERE------------------------------------------------------
---------------------------------------------------------------------------------------------------------------------------
�ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x1 (POWERON),boot:0xd (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
Any suggestions and help will be appreciated.
I am using IDF 4.3.2 release. I have also tried 4.4 release but the results are the same.
Top
ESP_Sprite
Posts: 9723
Joined: Thu Nov 26, 2015 4:08 am

Re: ESP32-C3-MINI-1U reboot loop when switching GPIO7

Postby ESP_Sprite » Thu Apr 07, 2022 12:59 am

That GPIO shouldn't have any pitfalls, but given the fact that you're switching a relay (which is an inductive load), I'd suspect either your power supply or EMC. Can you show your design (schematic / pcb layout) here?
Top
innomkr
Posts: 7
Joined: Wed Sep 22, 2021 4:29 am

Re: ESP32-C3-MINI-1U reboot loop when switching GPIO7

Postby innomkr » Thu Apr 14, 2022 10:45 am

Sorry, the issue was in hw. One of the diodes on the relay coils was soldered in the opposite way and was shorting the PSU when the GPIO is high. I didn't see that in first place because the device is consisted of 3 PCBs and this particular component wasn't visible without desoldering the PCBs
Top
Post Reply

Return to “ESP-IDF”

Who is online

Users browsing this forum: No registered users and 137 guests