How to keep MOSI line high at idle?

[gerard-hm]

My SPI setup:

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SPI_DEVICE_NO_DUMMY
SPI_DEVICE_3WIRE
SPI_DEVICE_HALFDUPLEX
no DMA
no interrupts (I use polling instead)
no address, no command phases, just data phase for a custom protocol

I'm currently using multiple DATA phases one after another with all 1s to simulate idle logic high, but there is still a small gap between the 64 bytes worth of DATA phases.

Is there a better, another way to keep MOSI line high at idle?

Some other hardware architectures apparently seem to hold the idle MOSI line at whatever level the last bit was sent, is there a way to have that behavior for ESP32?

thanks

[gerard-hm]

To answer my own question - the way to do it is to invert signal using:

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        esp_rom_gpio_connect_out_signal(mosi, spi_periph_signal[host_device].spid_out, invert, false);
        esp_rom_gpio_connect_in_signal(mosi, spi_periph_signal[host_device].spid_in, invert);

and then invert again all the data bytes:

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        buffer[i]  = ~data_byte; // invert