ESP32-S3 Peripheral Memory Mapping

[chintan_anrim]

Hi,

I need help understanding the memory mapping on the CPU for the ESP32-S3.

The SPI controller 0 and 1 (and most other peripherals) are assigned a 4K space in the CPU Address Map. But at the same time, the S3 supports an external flash device of upto 1G, which is connected over these SPI interfaces. Is the memory of the flash not directly mapped to the address space?

In my application the S3 is connected to an FPGA via the SPI interface (4 lanes). Can I map the registers in the FPGA into the address space of the processor (the 4K space allocated to the peripheral controller)?

Thanks,
Chintan

[WiFive]

No the flash is mapped to a virtual address space for external memory through the mmu/cache.

You have to access the fpga over spi, the only trick you could do would be get the fpga to emulate a flash or psram chip and use the mmu/cache to read/write to it.

[chintan_anrim]

Thanks for the reply.

So is the 4K memory that is mapped to each peripheral including the SPI Controller 0, 1 used for accessing internal registers needed to configure the peripheral.