IO Channels in multicore?

[cnlohr]

I'm having a lot of trouble figuring out exact timing with the IO channels when in multi-core mode.

It seems that provided you give at least a 12-instruction delay after the NMI is called, it's always predictable on a single core, regardless of what IO calls may be being made. (Haven't checked for things like execution from flash, etc.)

What I am running into though is trouble if the second core does any IO communication. It seems that I can bulldoze cpu1 IO with cpu0 IO in the NMI, but, there is jitter at the start, on the order of 100ns!

Is there any way to "claim" the IO interface for cpu0 inside the NMI to guarantee I get the least jitter as well as later on, being able to command the interface without fear of things getting wonky time-wise on me? I might only need to do that after I get the I2S engine going. I am still going back-and-forth over if I want to use the I2S engine for USB or raw GPIO, but, I will still need precise timing at the start of the interrupt either way I do it. Maybe just a "pause cpu1" for a couple cycles option?

Ooph. Trying to do IO on this thing is rough when both CPUs are sharing the same straw.

[ESP_igrr]

The easiest way would be to stall the other core and then go about your IO. However stalling the other core (via DPORT registers) would also go via an arbiter, so if the other core is accessing DPORT registers at the same time, there may be extra delay there.