How to deal with UART2 Tx FIFO "Garbrage after reset" bug.

[Baptisto]

Hello. Im stucket with UART Tx Fifo bug after soft reset.
It described here https://github.com/espressif/esp-idf/issues/5274
Im using IDF 4.0 with VisualGDB and cant change to higher version for now.

So im trying to make changes in my copy of IDF4.0, using the lastet fixes.
But commit, what must fix this issue in IDF4.2
https://github.com/espressif/esp-idf/co ... 98e4b80c6c

Only adds

Code: Select all

uart_hal_txfifo_rst(&(uart_context[uart_num].hal));

What leads us to

Code: Select all

static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
{
    if (hw == &UART0) {
        hw->conf0.txfifo_rst = 1;
        hw->conf0.txfifo_rst = 0;
    }
}

So... the only UART0 Tx Fifo may be reseted.
As i understand, there is no workaround for this bug, for UART2?

Im tried to set this bit on my UART0, after soft reset, but has no any result, UART2 Tx FIFO still has garbrage.

[WiFive]

https://github.com/espressif/esp-idf/co ... 098f7d40b2