From what I understand the ESP32 has 3 WDs - 2 MWDT and RWDT.
Does the RWDT or any other WD share the register memory with the ESP32 controller? or is it separated?
My concern is that memory overflow in the controller will change the registers of the WDs and the WDs will be useless in a case like that.
I would be glad for any answer concerning my question.
Best regards,
Elan
ESP32 WD
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Re: ESP32 WD
Yes, all WDTs have registers accessible from both CPUs. However, all WDTs have a 'lock' function, where writing to any register is ignored until a very specific 32-bit value is written to one of the registers. This also means the watchdog cannot be reset until the WDT registers are 'unlocked' this way. Chances of that happening 'by accident' because of a memory buffer overflow are negligably small.
Re: ESP32 WD
Thank you for the quick answer!
From what I saw the technical reference manual the watchdogs write protect section states that:
"On reset,these registers are initialized to the value 0x50D83AA1. When the value in this register is changed from
0x50D83AA1, write protection is enabled"
Is that what you meant? In order to change the WD I have to change the value from 0x50D83AA1 and thus the odds of that happening in memory overflow are small and the configruation of the WD are relatively safe?
In addition, i have 2 more question regarding the WDs:
1. How is the RTC_CLK built? Is it a simple RC circuit and is separated from the other clocks? The only reference I found is: "RTC_CLK is an internal low power clock with a default frequency of 150 KHz. This frequency is adjustable."
2. Would you say that the RTC WD is more "reliable" that the timer modules WDs because it can depend only on an clocks that are separated from the clocks generated in the ESP? for exapmle the RTC_CLK or the external 32KHz crystal.
From what I saw the technical reference manual the watchdogs write protect section states that:
"On reset,these registers are initialized to the value 0x50D83AA1. When the value in this register is changed from
0x50D83AA1, write protection is enabled"
Is that what you meant? In order to change the WD I have to change the value from 0x50D83AA1 and thus the odds of that happening in memory overflow are small and the configruation of the WD are relatively safe?
In addition, i have 2 more question regarding the WDs:
1. How is the RTC_CLK built? Is it a simple RC circuit and is separated from the other clocks? The only reference I found is: "RTC_CLK is an internal low power clock with a default frequency of 150 KHz. This frequency is adjustable."
2. Would you say that the RTC WD is more "reliable" that the timer modules WDs because it can depend only on an clocks that are separated from the clocks generated in the ESP? for exapmle the RTC_CLK or the external 32KHz crystal.
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- Posts: 9769
- Joined: Thu Nov 26, 2015 4:08 am
Re: ESP32 WD
Yes, that is what I meant. Wrt RTC WDT clock: Not sure of it's internal buildup (could be RC, could be something else) but it indeed is an entirely separate clock from the main 40MHz crystal or any 32KHz crystal in the system. The RTC WDT is more 'reliable' specifically for the purpose of pre-empting hardware issues with the system because of it's separate clock. For software problems, I'd say all WDTs are about equally useful.
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