SPI slave: MISO timing issue, data required earlier

[mupfelofen-de]

Hello,
I'm currently trying to solve a timing issue. My ESP32 is configured to be a SPI slave device. So in my current setup I get about every 16ms an active 12µs latch pulse (my CS), 6µs afterwards SCLK starts running. At the first clock pulse, MISO starts sending the data. So far, so good.

But the master requires the data 6µs earlier. Is there any way to do this? Unfortunately I do not have control over the master's latch or clock signal.

Here I tried to visualise the problem: https://paste.ubuntu.com/p/bgdM4BNGCq/

Any help is highly appreciated!

Greetings,
Michael