EFUSE read/write VDD_SDIO from user application

[WiFive]

Yes the bootloader has received some updates and is compiled from source when you run make.

What is your supply voltage?

@ESP_Angus any ideas?

[iosixllc]

Ok then I do have the latest bootloader. It seems if I could slow the write speed that would be ideal. I’m at 3.3V with VSDIO at 1.8V.

[ESP_Angus]

Hi ioxsillic,

Sorry I haven't been following this topic until now. It's possible running the flash at 3.3V for an extended period has caused some damage, although that's not a certainty.

Just to check I understand the problem:

• esptool.py always successfully flashes (as long as you have a new enough version).
• Booting at 80MHz DIO only works if voltage boosted to 3.3V. Booting at 40MHz DIO works at 1.8V.
• OTA updates fail at 40MHz DIO 1.8V, succeed at 40MHz DIO 3.3V.

Do I have this all correct?

Some quick questions:

• How many individual chips are you seeing this behaviour on? Have they all spent a prolonged period of time with flash voltage at 3.3V?
• If you lower the flash speed to 20MHz in menuconfig and re-flash the bootloader and app, does OTA succeed where it previously failed?
• I'm guessing you're using a custom PCB. How much capacitance do you have on power connections? If you monitor 3.3V VCC to the ESP32 during flashing, what kind of stability do you see?
• Do you have anything else connected to VDD_SDIO power domain I/Os (there's a diagram of these in the technical reference manual section 4.8, you can also find this information in the table at the very end of the ESP32 datasheet).

Thanks,

Angus

[ESP_Angus]

One other thing, can you please explain exactly what each value in the error log lines represent:

Code: Select all

E (107414) upgrade: Failed to write flash at address 0x0010621F, error 0 [380] 20702D3E = FFFFFFFF [1436]

(The address value seems to be the same each time is fails which is unexpected...?)

Thanks,

Angus

[iosixllc]

Thanks Angus,

Yes, you understand the problem correctly. We are seeing the behavior on ~30 chips, many of which were not ever run at 3.3V. 20MHz seems to have no effect. We have the standard 0.1uFs all around plus 1uF and 10uF near the antenna pad power inputs. Also, bulk 47uF capacitance maybe 10-20mm away. We don't have anything significant connected to VSDIO.

I was able to improve the problem significantly by lowering processor speed to 160MHz and replacing esp_ota_write with esp_partition_write and a verify step. It seems the second write cycle typically is able to write successfully, but is not possible with esp_ota_write as it automatically steps to the next block. Now it is working correctly. Thanks!

[WiFive]

How many blocks are you seeing fail the first write attempt?

[ESP_Angus]

replacing esp_ota_write with esp_partition_write and a verify step. It seems the second write cycle typically is able to write successfully, but is not possible with esp_ota_write as it automatically steps to the next block. Now it is working correctly.

So are you writing each sector twice now (ie erase once, then write twice)?