Correct. That's why you may want to use open drain mode.
For a better understanding, I suggest you look at the GPIO matrix and IOMUX in the TRM. It shows which settings/bits affect a pin at which level.
As I said: Tri-stating a pin means disabling its output, which is done via bits in the IOMUX's registers, not via the dedicated GPIO port of the CPU.but then how to clear bits, I can only write a bit.
Not really. There is no requirement for a register to read the same value which was written to it.If the input and output can co-exist then we need two registers for that, not one
For example, in the ESPs there are a few hardware FIFO buffers, each accessed via a single register so that a write enqueues data to be sent while a read retrieves data previously received.