If that was really necessary, you'd use gptimer_set_raw_count(...).
The exact frequency of the timer
-
- Posts: 1734
- Joined: Mon Oct 17, 2022 7:38 pm
- Location: Europe, Germany
Re: The exact frequency of the timer
-
- Posts: 1734
- Joined: Mon Oct 17, 2022 7:38 pm
- Location: Europe, Germany
Re: The exact frequency of the timer
How many bits in a row?
For short data bursts of a few bytes, busy-polling may be a good option (no CPU time "wasted" for entering and exiting the ISR), like
Code: Select all
uint32_t bit_cnt = byte_cnt * 10;
uint32_t start = esp_cpu_get_cycle_count();
for (uint32_t bit = bit_cnt; bit != 0; --bit) {
while( (esp_cpu_get_cycle_count() - start) < cpu_cycles_per_bit ) {
// Do nothing.
}
// Sample all 8 data lines, store result in buffer here.
start += cpu_cycles_per_bit; // Time for the next bit.
}
Re: The exact frequency of the timer
Thanks, I'll try.MicroController wrote: ↑Sat Sep 02, 2023 9:13 pmIf that was really necessary, you'd use gptimer_set_raw_count(...).
Re: The exact frequency of the timer
It is necessary to send 8 bytes of a common command to the sensors, and receive 11 bytes at the same time from 8 sensors. With a speed of 115200. And repeat all this with a frequency of 100 Hz.
-
- Posts: 1734
- Joined: Mon Oct 17, 2022 7:38 pm
- Location: Europe, Germany
Re: The exact frequency of the timer
And the data sent by all the sensors is synchronous and "in phase" to within a fraction of 1 bit?
Instead of using a timer at a fixed frequency, you can also investigate using the common GPIO interrupt (gpio_isr_register(...)) for all the RX signals; i.e., register all 8 input states + timestamp whenever any of the RX signals change. In the worst-case, this yields one (GPIO) interrupt per bit (e.g. when 0xAA is sent), but can avoid interrupts while no bits change (e.g. when 0xFF is sent). This also has the benefit of being "naturally" synchronized to the (start of the) RX signals.
However, 11 bytes is less than 1 ms @ 115200bps, so I wouldn't have too many concerns with trying the busy-polling approach which makes more CPU time available for processing each bit before the next one arrives, if that matters.
Instead of using a timer at a fixed frequency, you can also investigate using the common GPIO interrupt (gpio_isr_register(...)) for all the RX signals; i.e., register all 8 input states + timestamp whenever any of the RX signals change. In the worst-case, this yields one (GPIO) interrupt per bit (e.g. when 0xAA is sent), but can avoid interrupts while no bits change (e.g. when 0xFF is sent). This also has the benefit of being "naturally" synchronized to the (start of the) RX signals.
However, 11 bytes is less than 1 ms @ 115200bps, so I wouldn't have too many concerns with trying the busy-polling approach which makes more CPU time available for processing each bit before the next one arrives, if that matters.
-
- Posts: 9766
- Joined: Thu Nov 26, 2015 4:08 am
Re: The exact frequency of the timer
Just checking: the bitrate sounds suspiciously like something you should use an UART for... isn't that an option?
Re: The exact frequency of the timer
Yes, initially I planned to use a hardware UART. But it only works with one RX, and I need 8 at the same time. That is, so that each clock cycle is read not 1 bit, but 8 bits in parallel.ESP_Sprite wrote: ↑Mon Sep 04, 2023 1:14 amJust checking: the bitrate sounds suspiciously like something you should use an UART for... isn't that an option?
-
- Posts: 1734
- Joined: Mon Oct 17, 2022 7:38 pm
- Location: Europe, Germany
Re: The exact frequency of the timer
Timer-triggered GPIO DMA would be a great feature to have in future ESPs
Re: The exact frequency of the timer
I ran into such a problem: when issuing 8 bytes of a command sequentially through one GPIO on a timer, some other processes are periodically wedged into the process. As a result, timings are broken, and some commands are not recognized. How can I prohibit all other interrupts except the timer for the time of issuing the command? Not FreeRTOS, I haven't grown up to it yet. As simple as possible.
Re: The exact frequency of the timer
I disable interrupts via esp_intr_noniram_disable before forming the command and then turn it back on. It has become noticeably better, but there remains some process that blocks transmission for 40 ms once every 5 seconds. Disabled WDT in the config. What can influence this?
Who is online
Users browsing this forum: Bing [Bot], Sang_Huynh and 196 guests