rtc_clk_apll_enable函数调用失败

[ESP_igrr]

rtc_clk_apll_enable is used to enable/disable APLL (Audio PLL); Audio PLL can be used as a clock source for I2S peripheral. Not related to I2C

[WiFive]

To be more specific all the I2C references are related to the internal control bus, not i2c peripheral.

https://github.com/espressif/esp-idf/bl ... _clk.h#L29

[BuddyCasino]

To be more specific all the I2C references are related to the internal control bus, not i2c peripheral.

I see, thanks for the explanation. So when I call rtc_clk_apll_enable(), is it a "global" setting, or do I have to specifically connect it to the I2S clock domain somehow?

[WiFive]

I2S_CLKA_ENA Set this bit to enable clk_apll. (R/W)

https://github.com/espressif/esp-idf/bl ... i2s.c#L161

[Jakobsen]

Hi
To my understand on rev_0 hardware the APLL resolution is not good enough for generating a 2.8224 Mhz i2s clock due to bug on sdm1 and sdm0.
On rev_0 we can use normal PLL to generate i2s clock close to 2.822 MHz but it will have clock jitter. I did measurements on noise floor due to that clock jitter and hear a 16-18 dB higher audible noise floor compared to Raspberry PI2 setup.

When we have rev_1 device set enable and configure APLL for 2.822 MHz (or what ever we need) and let the i2s hardware use APLL clock as clock source - All that will just be done internal in the i2s driver layer.

Is that correct?
/j

[WiFive]

Hi
To my understand on rev_0 hardware the APLL resolution is not good enough for generating a 2.8224 Mhz i2s clock due to bug on sdm1 and sdm0.

Yes sounds right, my only question was in the meantime could you use APLL to get a better starting freq for I2S clock divider to achieve a marginal improvement of bck jitter or not worth it.

[BuddyCasino]

Alright then, where do you get the new rev1 chips from? Does the the DevkitC v2 always use the new revision? It seems to be sold out everywhere I looked.

[WiFive]

Rev1 not really available yet, only hint is some products quoting mid may.

[Jakobsen]

Hi All

Audio using normal PLL on rev_0 is OK for prototyping and to get the party started.

Your will hear a 'hiss' type noise if you dare to face ear close to speaker. But when your crank up the volume, noise it is covered.

Below 1KHz sine using 32 sample lookup table on ESP32 rev_0 PLL clock - 24bits@44.1k sample-rate in to Merus audio digital input power amplifier (MA12040P)


Below raspberry pi2 i2s output same setup. Only noise floor. Raspberry Pi2 not considered audiophile due to clock jitter on i2s_bck!


/j