ESP32-S3 with RGB interface LCD - lagging/delay in screen rendering issue

[tushar@esp]

Hi There,

We are working on ESP-S3 with RGB interface TFT LCD display. We have [ESP32-S3-RGB][https://www.aliexpress.com/item/3256803 ... 4itemAdapt] development Kit and we are running some examples from [ESP32-S3-RGB-Panel][https://github.com/W00ng/ESP32-S3-RGB-Panel]. This board has ESP32-S3R8(Internal 8MB Psram)+ 8MB FLASH(external).
We are seeing the lagging/delay in screen rendering while changing the screens or while scrolling. As per the manufacturer of this board, this is a PSRAM speed issue.

Environment:
MCU: ESP32-S3R8
ESP-IDF: v4.4.1
Chip revision: 0
Host: windows 10

Note: Below(attached) image is my sample application configuration regarding SPIRAM i.e PSRAM.
Can someone please help on this UI screen lagging issue?

image.png (78.61 KiB) Viewed 7787 times

[ESP_Sprite]

You could try to set both PSRAM and flash speed to 120MHz, that should give you an extra boost. (Also check if the CPU speed is 240MHz.) If you end up designing your own hardware, you can go for a chip with octal PSRAM, that is even faster.

[tushar@esp]

Hi,
CPU speed is already 240MHz and SPI RAM it is already configured as Octal mode.
Able to set external flash speed to 120MHz but for SPIRAM(PSRAM) there is only 40 and 80 MHz option in the menuconfig.
If I made it forcefully in sdkconfig file, it gives below error at compile time.

Code: Select all

In file included from C:/Espressif/frameworks/esp-idf-v4.4.1/components/spi_flash/spi_flash_timing_tuning.c:19:
C:/Espressif/frameworks/esp-idf-v4.4.1/components/spi_flash/esp32s3/spi_timing_config.h:174:1: error: static assertion failed: "FLASH and PSRAM Mode configuration are not supported"
 _Static_assert(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_PSRAM_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported");
 ^~~~~~~~~~~~~~

And this is points to below code section, and it mentioning some limitation. so, can you please tell me how can we configure 120MHz for SPIRAM?

Code: Select all

//------------------------------------------Determine the Core Clock-----------------------------------------------//
/**
 * @note
 * Limitation 1:
 * On 728, MSPI FLASH and PSRAM share the core clock register. Therefore,
 * the expected CORE CLOCK frequencies should be the same.
 */
#if SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING
_Static_assert(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ, "FLASH and PSRAM Mode configuration are not supported");
#define SPI_TIMING_CORE_CLOCK_MHZ                   SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ

//If only FLASH needs tuning, the core clock COULD be as FLASH expected
#elif SPI_TIMING_FLASH_NEEDS_TUNING && !SPI_TIMING_PSRAM_NEEDS_TUNING
_Static_assert(SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ % SPI_TIMING_PSRAM_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported");
#define SPI_TIMING_CORE_CLOCK_MHZ                   SPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ

//If only PSRAM needs tuning, the core clock COULD be as PSRAM expected
#elif !SPI_TIMING_FLASH_NEEDS_TUNING && SPI_TIMING_PSRAM_NEEDS_TUNING
_Static_assert(SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % SPI_TIMING_FLASH_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported");
#define SPI_TIMING_CORE_CLOCK_MHZ                   SPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ

#else
#define SPI_TIMING_CORE_CLOCK_MHZ   80
#endif

/**
 * @note
 * Limitation 2: DDR mode requires the core clock divider (core_clk / div = module_clk) to be power of 2.
 */
#define CHECK_POWER_OF_2(n)                         ((((n) & ((~(n)) + 1))) == (n))

#if SPI_TIMING_FLASH_DTR_MODE
_Static_assert(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_FLASH_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported");
#endif
#if SPI_TIMING_PSRAM_DTR_MODE
_Static_assert(CHECK_POWER_OF_2(SPI_TIMING_CORE_CLOCK_MHZ / SPI_TIMING_PSRAM_MODULE_CLOCK), "FLASH and PSRAM Mode configuration are not supported");
#endif

[ESP_Sprite]

Sorry, I missed that you were already running octal psram; in that case 80Mhz is the max (but since it's DDR, it's still 3x as fast as 120MHz quad PSRAM)

[tushar@esp]

Hi,
so, Is octal mode limited to 80MHz only?
If this is the case, then I did the maximum configuration required. Still, I am getting significant delay in changing the screens or while scrolling on RGB interface display.
So, Is there any solution for this? Is there any example for PSRAM optimized use? Can you suggest any other configuration to achieve smooth experience on RGB interface?

Best regards and thanks for your time.

[tushar@esp]

I also have ESP32-S3-BOX board. When I walked through Hardware overview for the same at https://github.com/espressif/esp-box/bl ... for_box.md, I found that it supports PSRAM with 120MHz of speed with octal mode.

But when I checked the sdkconfig file for examples from https://github.com/espressif/esp-box, I found that it is configured as 80MHz only.
So, Is there a way to configure PSRAM as 120MHZ speed for octal mode?

[ESP_Sprite]

No, there is not. For octal PSRAM, there's two transfers every clock cycle, so selecting '80MHz' for octal psram already runs it faster than 120MHz for quad psram (160 Mtransfers/sec vs 120 Mtransfers/sec)

Also, that spec is... misleading at best. The PSRAM itself may physically be able to run at 120MHz in some mode, but the ESP32-S3 does not support that. I've asked the doc team to take a look at that and fix it.

What is the PCLK frequency of your LCD, if I may ask? Also, in menuconfig under 'Component config → ESP PSRAM → Support for external, SPI-connected RAM → SPI RAM config', have you tried enabling 'Cache fetch instructions from psram' and 'cache load read only data from psram'? As on your devboard, psram is four times as fast as flash, this may give you some extra speed.

[tushar@esp]

The PCLK frequency of LCD is 10MHz. Please find the other parameter of the LCD that we are setting to register new LCD in func esp_lcd_new_rgb_panel.

Code: Select all

esp_lcd_rgb_panel_config_t panel_config = {
.timings = {
            .pclk_hz = 10 * 1000 * 1000,
            .h_res = LCD_WIDTH,
            .v_res = LCD_HEIGHT,
            // The following parameters should refer to LCD spec
            .hsync_back_porch = 50,
            .hsync_front_porch = 10,
            .hsync_pulse_width = 8,
            .vsync_back_porch = 20,
            .vsync_front_porch = 10,
            .vsync_pulse_width = 8,
            .flags.pclk_active_neg = 0, // RGB data is clocked out on falling edge
        },
}
esp_lcd_new_rgb_panel(&panel_config, &panel_handle);

I tried option 'Cache fetch instructions from psram' and 'cache load read only data from psram', no change in result.

Let me know if there is any other configuration that can help to get me better UI experience?
I wanted to upload the video to show the lagging issue, but not seeing any option to upload the video in forum. If it is, please let me know.

[ESP_YWxpYw]

0001-spi_flash-abstract-spi1-tuning-functions.patch.txt

(24.43 KiB) Downloaded 375 times

This is a patch that provides 120MHz PSRAM feature based on esp-idf commit id c2ccc383dae2a47c2c2dc8c7ad78175a3fd11361. With this patch, you can select the frequency of PSRAM and FLASH in menuconfig as 120MHz.

You can apply the patch using the following command:

Code: Select all

git checkout c2ccc383da
git apply  0001-spi_flash-abstract-spi1-tuning-functions.patch.txt

Attention: The new feature of 120MHz PSRAM has not passed the high temperature test completely, so it has not been merged into the master branch of IDF, therefore it should be noted that the high temperature environment may be unstable when using it.

[tushar@esp]

Even with the latest master IDF (c2ccc383da), I am able to see good results with the 80MHz speed option, compared to IDF 4.4.

For 120MHz and other optimization, ESP FAE has shared https://glab.espressif.cn/esp-solution/ ... sp-lcd-rgb as a current development branch and we are doing experiments on this for now.