I am having a few issues when I try to set the data cache to 16kb on the S3.
I am on IDF 4.4.1
Issue 1: If at the same time, I enable CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP, then there is a compile error in esp32s3/memory_layout.c, I think there is a missing trailing comma in line 75. For now, apparently these two options are mutually exclusive, is that the intended behaviour?
Issue 2: When configured to run more than 1 core, the system becomes extremely unstable. If I limit it to one core everything seems to run smoothly, but as soon as I add in the second core, I get intermittent reboots, as for example (I dont know why the stack pointer is pointing to the top of the RTC RAM, this looks so weird):
Is the 16KB data cache not supported on dual CPU?Guru Meditation Error: Core 1 panic'ed (Double exception).
Core 1 register dump:
PC : 0x4038ad47 PS : 0x00040136 A0 : 0xbad00bad A1 : 0x60100000
0x4038ad47: _xt_context_save at components/freertos/port/xtensa/xtensa_context.S:195
A2 : 0x00040136 A3 : 0x00040026 A4 : 0x00000000 A5 : 0x00000000
A6 : 0x00000001 A7 : 0x00002000 A8 : 0x8037b990 A9 : 0x00000000
A10 : 0x3fcaa24c A11 : 0x00000000 A12 : 0x00000000 A13 : 0x00000000
A14 : 0x3fcab134 A15 : 0x007f9798 SAR : 0x00000004 EXCCAUSE: 0x00000002
EXCVADDR: 0x00000000 LBEG : 0x400556d5 LEND : 0x400556e5 LCOUNT : 0xffffffff
Backtrace:0x4038ad44:0x60100000 |<-CORRUPTED
0x4038ad44: _xt_context_save at components/freertos/port/xtensa/xtensa_context.S:194
As a side note: I had to edit panic_handler.c to comment out these two lines to even get the above register dump, as otherwise the WDT kicked in:
Kind regardsBUSY_WAIT_IF_TRUE(panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU0 && core_id == 1);
BUSY_WAIT_IF_TRUE(panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU1 && core_id == 0);
Mikkel