ESP32-S3 Hardware Design Guidelines | 硬件设计指南

[rudi ;-)]

Hi Folks,

Hardware design guidelines give advice on how to integrate ESP32-S3 into other products.
ESP32-S3 is a series of high-performance Wi-Fi and Bluetooth® 5 (LE) SoCs.
These guidelines will help to ensure optimal performance of your product with respect to tech-
nical accuracy and conformity to Espressif’s standards.

ESP32­-S3 Hardware Design Guidelines
The hardware design guidelines give advice on how to integrate ESP32-S3 into other products.
v1.0 2021.09.30


本文提供基于 ESP32-S3 的硬件设计的指导规范。ESP32-S3 是一款具有超高性能的 Wi-Fi +
Bluetooth® 5 (LE) 系统级芯片。
这些规范将帮助您提升电路和 PCB 版图设计的准确性。

ESP32-S3 硬件设计指南
本文提供基于 ESP32-S3 的硬件设计的指导规范。
v1.0 2021年09月30日

also for History here attached EN and CN Version

EN

esp32-s3_hardware_design_guidelines_en.pdf

ESP32­-S3 Hardware Design Guidelines
v1.0 2021.09.30

(1.19 MiB) Downloaded 1125 times

CN

esp32-s3_hardware_design_guidelines_cn.pdf

ESP32-S3 硬件设计指南
本文提供基于 ESP32-S3 的硬件设计的指导规范。
v1.0 2021年09月30日

(1.55 MiB) Downloaded 1033 times

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best wishes
rudi

[twicejiggled]

Hi Rudi,

Thanks for posting this!

On page 12, section 2.5 RF of the esp32-s3 hardware guidelines it doesn't specify the pin impedance for the esp32s3 QFN 7x7 56 pin package, compared to the esp32 guidelines (https://www.espressif.com/sites/default ... nes_en.pdf) which specify " output impedance of the RF pins of ESP32 (QFN 6*6) and ESP32 (QFN 5*5) are (30+j10) Ω and (35+j10) Ω,
respectively".

Is the impedance known for the s3, or could you recommend a pi circuit and CL filter to match with the s3 on standard FR4 2 layer 1oz copper?

Any comments or help would be greatly appreciated,

Liam