Hi guys,
I have a custom EPS32-Pico D4 board for a project of mine. The board was developed by a third party, so I did not design the board by myself. I am a mechanical engineer and therefore the PCB design process is kind of out of my scope of knowledge. Nevertheless, I still hope, that you guys are willing to help me out with the problem I'm facing. The board itself was produced and assembled by PCBway, I ordered 10 boards in total.
The Problem:
Since end of 2021 I am trying to upload a sketch to the board, but it always fails with the same error message in Arduino:
___________________________
esptool.py v3.0-dev
Serial port /dev/cu.usbserial-0001
Connecting........_____.
Chip is ESP32-PICO-D4 (revision 1)
Features: WiFi, BT, Dual Core, 240MHz, Embedded Flash, VRef calibration in efuse, Coding Scheme None
Crystal is 40MHz
MAC: 30:83:98:e0:7d:f0
Uploading stub...
Running stub...
Stub running...
Configuring flash size...
Warning: Could not auto-detect Flash size (FlashID=0x0, SizeID=0x0), defaulting to 4MB
Compressed 8192 bytes to 47...
Writing at 0x0000e000... (100 %)
Wrote 8192 bytes (47 compressed) at 0x0000e000 in 0.0 seconds (effective 7913.1 kbit/s)...
A fatal error occurred: Timed out waiting for packet header
A fatal error occurred: Timed out waiting for packet header
___________________________
- I tried different settings: Board (ESP32 Dev Module/ ESP32 Pico Kit), Upload Speed (115200-921600 baud rates), Flash frequency (40/80 Mhz), Flash Mode (QIO/DIO/QOUT/DOUT). Despite the different settings, the error message remains the same.
- I tried to put the microcontroller into boot mode with the EN and BOOT button procedure, but that had no effect.
- I checked all pins for the flash communication, all are left free, which is also visible in the schematics I attached.
- I tried programming it via Arduino on Mac as well as windows, same error persists.
- No matter which code I upload, the error message is the same.
- I have the same behavior with each of the 10 boards, so I would think, that this is not an assembly error.
- I also tried to communicate with the board through esp.py via terminal but the output also gives me a warning, that it is not able to communicate with the flash. I attached the terminal output, maybe this is helpful for anybody.
- While searching for similar problems in this forum, I found a post (https://www.esp32.com/viewtopic.php?t=16192#p61610) where it is suggested, that the GND solder plate could be the problem, but I have no idea if that is also the case for my pcb. I attached a photo of an unassembled platine of that pcb, maybe you can tell me if that looks like a proper GND connection for the PICO-D4 or not, because I am not able to determine that by myself.
I also tried contacting The PCB designer, but he has not been able to find what is wrong and can't help me out regarding this problem, so you are kind of my last hope to find the error. I am more than willing to learn and do everything to test or further debug the problem, but I have no clue at the moment how to go from here. Please let me know, if I can do anything to help find the problem.
I hope I did not forget any information, if I did, please get back to me and I will try to provide everything necessary.
I really appreciate your help, thank you all in advance,
Dario
Custom ESP32-PICO-D4 board, not able to upload sketches (no communication to internal flash)
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- Posts: 9764
- Joined: Thu Nov 26, 2015 4:08 am
Re: Custom ESP32-PICO-D4 board, not able to upload sketches (no communication to internal flash)
Your GPIO12 is connected to a sensor. If that sensor outputs a high when the ESP32 boots up, the ESP32 uses an internal flash voltage of 1.8V, which is unlikely to work. You can try to either ground that while you upload, or use espefuse.py to burn the fuse to force the flash voltage to be 3.3V.
Re: Custom ESP32-PICO-D4 board, not able to upload sketches (no communication to internal flash)
Hi ESP_Sprite,
thanks for your message.
Regarding Setting GPIO12 to low: I have already tried scratching the copper layer off of the pcb on the path to the sensor to disconnect the sensor from GPIO12. I though this way, I could assure that GPIO12 is in any case set to low, please correct me if I am wrong and still need to connect GPIO12 to GND to achieve a low signal on that pin.
Regarding espefuse.py: I just burned the efuse with this command: espefuse.py --port /dev/cu.usbserial-0001 set_flash_voltage 3.3V (Source: https://docs.espressif.com/projects/esp ... index.html), but I am still facing the same error message. So I either did the efuse wrong or that sadly is not the solution for my problem. Maybe I have to additionally efuse something else? Below you will find the summary and dump once before efuse and also afterwards. One can see, that the efuse command changed the voltage regulator to 3.3V:
espefuse.py summary BEFORE EFUSE:
MBPs-MBP:~ dario$ espefuse.py --port /dev/cu.usbserial-0001 summary
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting....
Detecting chip type... ESP32
espefuse.py v3.2
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Calibration fuses:
BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
ADC_VREF (BLOCK0): Voltage reference calibration = 1135 R/W (0b00101)
Config fuses:
XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = True R/W (0b1)
XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0)
XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0)
CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 53 R/W (0x35)
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 6 R/W (0b00110)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 17 R/W (0b10001)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 8 R/W (0b01000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 11 R/W (0b01011)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 16 R/W (0b10000)
DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
Efuse fuses:
WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000)
RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0)
CODING_SCHEME (BLOCK0): Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
Identity fuses:
MAC (BLOCK0): Factory MAC Address
= 30:83:98:e0:7e:20 (CRC 0x1b OK) R/W
MAC_CRC (BLOCK0): CRC8 for factory MAC address = 27 R/W (0x1b)
CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0)
CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
CHIP_PACKAGE (BLOCK0): Chip package identifier = 5 R/W (0b101)
MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
Security fuses:
FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000)
UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0)
CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0)
JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0)
DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0)
DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0)
BLOCK1 (BLOCK1): Flash encryption key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK2 (BLOCK2): Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3): Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Flash voltage (VDD_SDIO) internal regulator disabled by efuse.
MBPs-MBP:~ dario$ espefuse.py --port /dev/cu.usbserial-0001 dump
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting....
Detecting chip type... ESP32
BLOCK0 ( ) [0 ] read_regs: 00000000 98e07e20 001b3083 0000aab0 00010535 00082226 00000004
BLOCK1 (flash_encryption) [1 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK2 (secure_boot_v1 s) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK3 ( ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
EFUSE_REG_DEC_STATUS 0x00000000
espefuse.py v3.2
Efuse Command and terminal output:
MBPs-MBP:~ dario$ espefuse.py --port /dev/cu.usbserial-0001 set_flash_voltage 3.3V
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting....
Detecting chip type... ESP32
espefuse.py v3.2
Enable internal flash voltage regulator (VDD_SDIO) to 3.3V.
The following efuses are burned: XPD_SDIO_FORCE, XPD_SDIO_REG, XPD_SDIO_TIEH.
The same value for XPD_SDIO_FORCE is already burned. Do not change the efuse.
VDD_SDIO setting complete.
Check all blocks for burn...
idx, BLOCK_NAME, Conclusion
[00] BLOCK0 is not empty
(written ): 0x0000000400082226000105350000aab0001b308398e07e2000000000
(to write): 0x00000000000000000000c00000000000000000000000000000000000
(coding scheme = NONE)
.
This is an irreversible operation!
Type 'BURN' (all capitals) to continue.
BURN
BURN BLOCK0 - OK (all write block bits are set)
Reading updated efuses...
espefuse.py summary AFTER EFUSE:
MBPs-MBP:~ dario$ espefuse.py --port /dev/cu.usbserial-0001 summary
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting....
Detecting chip type... ESP32
espefuse.py v3.2
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Calibration fuses:
BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
ADC_VREF (BLOCK0): Voltage reference calibration = 1135 R/W (0b00101)
Config fuses:
XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = True R/W (0b1)
XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = True R/W (0b1)
XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 3.3V R/W (0b1)
CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 53 R/W (0x35)
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 6 R/W (0b00110)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 17 R/W (0b10001)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 8 R/W (0b01000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 11 R/W (0b01011)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 16 R/W (0b10000)
DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
Efuse fuses:
WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000)
RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0)
CODING_SCHEME (BLOCK0): Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
Identity fuses:
MAC (BLOCK0): Factory MAC Address
= 30:83:98:e0:7e:20 (CRC 0x1b OK) R/W
MAC_CRC (BLOCK0): CRC8 for factory MAC address = 27 R/W (0x1b)
CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0)
CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
CHIP_PACKAGE (BLOCK0): Chip package identifier = 5 R/W (0b101)
MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
Security fuses:
FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000)
UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0)
CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0)
JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0)
DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0)
DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0)
BLOCK1 (BLOCK1): Flash encryption key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK2 (BLOCK2): Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3): Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Flash voltage (VDD_SDIO) set to 3.3V by efuse.
MBPs-MBP:~ dario$ espefuse.py --port /dev/cu.usbserial-0001 dump
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting....
Detecting chip type... ESP32
BLOCK0 ( ) [0 ] read_regs: 00000000 98e07e20 001b3083 0000aab0 0001c535 00082226 00000004
BLOCK1 (flash_encryption) [1 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK2 (secure_boot_v1 s) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK3 ( ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
EFUSE_REG_DEC_STATUS 0x00000000
espefuse.py v3.2
Is there anything else I could try or does any of the values given in the summary seem odd to you? I wonder if these values:
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 6 R/W (0b00110)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 17 R/W (0b10001)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 8 R/W (0b01000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 11 R/W (0b01011)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 16 R/W (0b10000)
should rather be all 0, than 6/17/8/11/16, but this is just a wild guess and I would certainly not know how to manipulate these either by hardware or software.
Thanks & Best regards,
Dario
thanks for your message.
Regarding Setting GPIO12 to low: I have already tried scratching the copper layer off of the pcb on the path to the sensor to disconnect the sensor from GPIO12. I though this way, I could assure that GPIO12 is in any case set to low, please correct me if I am wrong and still need to connect GPIO12 to GND to achieve a low signal on that pin.
Regarding espefuse.py: I just burned the efuse with this command: espefuse.py --port /dev/cu.usbserial-0001 set_flash_voltage 3.3V (Source: https://docs.espressif.com/projects/esp ... index.html), but I am still facing the same error message. So I either did the efuse wrong or that sadly is not the solution for my problem. Maybe I have to additionally efuse something else? Below you will find the summary and dump once before efuse and also afterwards. One can see, that the efuse command changed the voltage regulator to 3.3V:
espefuse.py summary BEFORE EFUSE:
MBPs-MBP:~ dario$ espefuse.py --port /dev/cu.usbserial-0001 summary
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting....
Detecting chip type... ESP32
espefuse.py v3.2
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Calibration fuses:
BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
ADC_VREF (BLOCK0): Voltage reference calibration = 1135 R/W (0b00101)
Config fuses:
XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = True R/W (0b1)
XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0)
XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0)
CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 53 R/W (0x35)
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 6 R/W (0b00110)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 17 R/W (0b10001)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 8 R/W (0b01000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 11 R/W (0b01011)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 16 R/W (0b10000)
DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
Efuse fuses:
WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000)
RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0)
CODING_SCHEME (BLOCK0): Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
Identity fuses:
MAC (BLOCK0): Factory MAC Address
= 30:83:98:e0:7e:20 (CRC 0x1b OK) R/W
MAC_CRC (BLOCK0): CRC8 for factory MAC address = 27 R/W (0x1b)
CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0)
CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
CHIP_PACKAGE (BLOCK0): Chip package identifier = 5 R/W (0b101)
MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
Security fuses:
FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000)
UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0)
CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0)
JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0)
DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0)
DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0)
BLOCK1 (BLOCK1): Flash encryption key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK2 (BLOCK2): Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3): Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Flash voltage (VDD_SDIO) internal regulator disabled by efuse.
MBPs-MBP:~ dario$ espefuse.py --port /dev/cu.usbserial-0001 dump
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting....
Detecting chip type... ESP32
BLOCK0 ( ) [0 ] read_regs: 00000000 98e07e20 001b3083 0000aab0 00010535 00082226 00000004
BLOCK1 (flash_encryption) [1 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK2 (secure_boot_v1 s) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK3 ( ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
EFUSE_REG_DEC_STATUS 0x00000000
espefuse.py v3.2
Efuse Command and terminal output:
MBPs-MBP:~ dario$ espefuse.py --port /dev/cu.usbserial-0001 set_flash_voltage 3.3V
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting....
Detecting chip type... ESP32
espefuse.py v3.2
Enable internal flash voltage regulator (VDD_SDIO) to 3.3V.
The following efuses are burned: XPD_SDIO_FORCE, XPD_SDIO_REG, XPD_SDIO_TIEH.
The same value for XPD_SDIO_FORCE is already burned. Do not change the efuse.
VDD_SDIO setting complete.
Check all blocks for burn...
idx, BLOCK_NAME, Conclusion
[00] BLOCK0 is not empty
(written ): 0x0000000400082226000105350000aab0001b308398e07e2000000000
(to write): 0x00000000000000000000c00000000000000000000000000000000000
(coding scheme = NONE)
.
This is an irreversible operation!
Type 'BURN' (all capitals) to continue.
BURN
BURN BLOCK0 - OK (all write block bits are set)
Reading updated efuses...
espefuse.py summary AFTER EFUSE:
MBPs-MBP:~ dario$ espefuse.py --port /dev/cu.usbserial-0001 summary
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting....
Detecting chip type... ESP32
espefuse.py v3.2
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Calibration fuses:
BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
ADC_VREF (BLOCK0): Voltage reference calibration = 1135 R/W (0b00101)
Config fuses:
XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = True R/W (0b1)
XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = True R/W (0b1)
XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 3.3V R/W (0b1)
CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 53 R/W (0x35)
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 6 R/W (0b00110)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 17 R/W (0b10001)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 8 R/W (0b01000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 11 R/W (0b01011)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 16 R/W (0b10000)
DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
Efuse fuses:
WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000)
RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0)
CODING_SCHEME (BLOCK0): Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
Identity fuses:
MAC (BLOCK0): Factory MAC Address
= 30:83:98:e0:7e:20 (CRC 0x1b OK) R/W
MAC_CRC (BLOCK0): CRC8 for factory MAC address = 27 R/W (0x1b)
CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0)
CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
CHIP_PACKAGE (BLOCK0): Chip package identifier = 5 R/W (0b101)
MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
Security fuses:
FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000)
UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0)
CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0)
JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0)
DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0)
DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0)
BLOCK1 (BLOCK1): Flash encryption key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK2 (BLOCK2): Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3): Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Flash voltage (VDD_SDIO) set to 3.3V by efuse.
MBPs-MBP:~ dario$ espefuse.py --port /dev/cu.usbserial-0001 dump
Connecting....
Detecting chip type... Unsupported detection protocol, switching and trying again...
Connecting....
Detecting chip type... ESP32
BLOCK0 ( ) [0 ] read_regs: 00000000 98e07e20 001b3083 0000aab0 0001c535 00082226 00000004
BLOCK1 (flash_encryption) [1 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK2 (secure_boot_v1 s) [2 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
BLOCK3 ( ) [3 ] read_regs: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
EFUSE_REG_DEC_STATUS 0x00000000
espefuse.py v3.2
Is there anything else I could try or does any of the values given in the summary seem odd to you? I wonder if these values:
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 6 R/W (0b00110)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 17 R/W (0b10001)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 8 R/W (0b01000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 11 R/W (0b01011)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 16 R/W (0b10000)
should rather be all 0, than 6/17/8/11/16, but this is just a wild guess and I would certainly not know how to manipulate these either by hardware or software.
Thanks & Best regards,
Dario
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- Posts: 9764
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Re: Custom ESP32-PICO-D4 board, not able to upload sketches (no communication to internal flash)
No, those fuses are OK; they're set as the Pico-D4 uses different pins for the flash than a 'normal' ESP32.
I'm not seeing anything else wrong with your setup from the schematic side of things. Still, your symptoms clearly indicate that the ESP32 is working, but there's a problem in communicating with the internal flash. Do you have the tools to measure if any of the flash pins (25,27,30-33) is shorted or connected to ground?
I'm not seeing anything else wrong with your setup from the schematic side of things. Still, your symptoms clearly indicate that the ESP32 is working, but there's a problem in communicating with the internal flash. Do you have the tools to measure if any of the flash pins (25,27,30-33) is shorted or connected to ground?
Re: Custom ESP32-PICO-D4 board, not able to upload sketches (no communication to internal flash)
IO2 is pulled up, you will need it low to program successfully
Re: Custom ESP32-PICO-D4 board, not able to upload sketches (no communication to internal flash)
Hi,
thank you both for your replies. Before measuring the internal flash pins I tried also pulling down the IO2 pin as boarchuz suggested and I finally got it to upload the sketch, which is amazing!! In the end for my board it was needed to just pull down (connect to GND) the GPIO12 and GPIO2 pins. I tested it with another board which was not "efused" by me in before and the upload finished without an error. (even with the 921600 baud rate).
Thank you both again for your kind and fast help, I appreciate it a lot!
Best regards,
Dario
thank you both for your replies. Before measuring the internal flash pins I tried also pulling down the IO2 pin as boarchuz suggested and I finally got it to upload the sketch, which is amazing!! In the end for my board it was needed to just pull down (connect to GND) the GPIO12 and GPIO2 pins. I tested it with another board which was not "efused" by me in before and the upload finished without an error. (even with the 921600 baud rate).
Thank you both again for your kind and fast help, I appreciate it a lot!
Best regards,
Dario
-
- Posts: 9764
- Joined: Thu Nov 26, 2015 4:08 am
Re: Custom ESP32-PICO-D4 board, not able to upload sketches (no communication to internal flash)
Now I feel stupid for not catching that. Good eye, boarchuz!
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