D0WD D2WD WROOM-32 WROVER deep sleep SPI Flash pSRAM

[rudi ;-)]

hi ESP_*+guys

after several studdy now we have this fixed question:

a) deep sleep with 5µA is possible if we set VDD_SDIO to 1.8V right?
b) ESP32-D0WD is driven by 3.3V and can setup VDD_SDIO to 1.8V and 3.3V right?
c) ESP32-D2WD is driven by 3.3V and intern Flash is driven by 1.8V right?
d) ESP32-D2WD must then set bootstrap to high or using efuse that intern Flash is driven by 1.8V right?
e) all WROOM-32 on the market are using 3.3V SPI Flash right?
f) ESP-pSRAM32 can be driven from 1.8V do 3.3V and need not to drive 1.8V and can be driven with 3.3V right?
g) if we combine ESP32-D0WD with ESP-pSRAM32 we can use it on 3.3V if we use SPI Flash 3.3V ic's
h) if we combine ESP32-D2WD with ESP-pSRAM32 we must use 1.8V cause intern Flash and ESP-pSRAM32 share Dataline PINS
i) if we combine ESP32-D0WD with ESP-pSRAM32 we use same sharing DATAPINS and can driven by 3.3V
j) if we combine over Sharing Datapins - we set on ESP32-D0WD only /CS and CLK to other Pins from ESP-pSRAM32

i wounder too,
WROVER Modules are based on *j) - the comming outs are ( grounded deep sleep 5µA ) with SPI Flash 1.8V and drive ESP-pSRAM32 with 1.8V too over VDD_SDIO - right?

WROOM32 modules are based on *j) or based on 3.3V ? this is important for production boards in future,
so without answeres there is no planing possible too.

thank you

[WiFive]

I not a esp_ guy but I can guess

a) deep sleep with 5µA is possible if we set VDD_SDIO to 1.8V right?
Yes deep sleep vdd_sdio is off so voltage shouldn't matter

b) ESP32-D0WD is driven by 3.3V and can setup VDD_SDIO to 1.8V and 3.3V right?
Yes

c) ESP32-D2WD is driven by 3.3V and intern Flash is driven by 1.8V right?
d) ESP32-D2WD must then set bootstrap to high or using efuse that intern Flash is driven by 1.8V right?
Yes I think efuse set to 1.8v vdd_sdio at factory

e) all WROOM-32 on the market are using 3.3V SPI Flash right?
AFAIK

f) ESP-pSRAM32 can be driven from 1.8V do 3.3V and need not to drive 1.8V and can be driven with 3.3V right?
g) if we combine ESP32-D0WD with ESP-pSRAM32 we can use it on 3.3V if we use SPI Flash 3.3V ic's
i) if we combine ESP32-D0WD with ESP-pSRAM32 we use same sharing DATAPINS and can driven by 3.3V
Have a feeling it is 1.8v only. Lyontek have separate parts for 1.8&3.3

h) if we combine ESP32-D2WD with ESP-pSRAM32 we must use 1.8V cause intern Flash and ESP-pSRAM32 share Dataline PINS
Yes

j) if we combine over Sharing Datapins - we set on ESP32-D0WD only /CS and CLK to other Pins from ESP-pSRAM32
Yes

[ESP_igrr]

c) ESP32-D2WD is driven by 3.3V and intern Flash is driven by 1.8V right?
d) ESP32-D2WD must then set bootstrap to high or using efuse that intern Flash is driven by 1.8V right?
Yes I think efuse set to 1.8v vdd_sdio at factory

Efuse for 1.8V is not set in factory, at least for now. If this is changed in the future, we will add a note to the datasheet.

e) all WROOM-32 on the market are using 3.3V SPI Flash right?
AFAIK

One can order 1.8V WROOM-32, subject to MOQ.

f) ESP-pSRAM32 can be driven from 1.8V do 3.3V and need not to drive 1.8V and can be driven with 3.3V right?

will check this on Monday...

h) if we combine ESP32-D2WD with ESP-pSRAM32 we must use 1.8V cause intern Flash and ESP-pSRAM32 share Dataline PINS

I'm not sure whether this is a supported combination — IIRC the internal flash uses some pins which we also use for CS & CLK for pSRAM.

[WiFive]

Efuse for 1.8V is not set in factory, at least for now. If this is changed in the future, we will add a note to the datasheet.

Oh oops. SPI pin remap fuses are set but not vdd_sdio? Does that mean internal flash is connected to internal 1.8v ldo upstream of vdd_sdio pad? Or is it mandatory to operate in vdd_sdio = 1.8v even though fuse is not set?

h) if we combine ESP32-D2WD with ESP-pSRAM32 we must use 1.8V cause intern Flash and ESP-pSRAM32 share Dataline PINS

I'm not sure whether this is a supported combination — IIRC the internal flash uses some pins which we also use for CS & CLK for pSRAM.

Hmm well we still have 2 free pins in sdio domain unless something special about 16&17.

[rudi ;-)]

f) ESP-pSRAM32 can be driven from 1.8V do 3.3V and need not to drive 1.8V and can be driven with 3.3V right?

will check this on Monday...

ivan VDD is 1.8V

h) if we combine ESP32-D2WD with ESP-pSRAM32 we must use 1.8V cause intern Flash and ESP-pSRAM32 share Dataline PINS

I'm not sure whether this is a supported combination — IIRC the internal flash uses some pins which we also use for CS & CLK for pSRAM.

how are this pins max in voltage ivan?
CS and CLK are outputs from esp32
and on high state 3.3V or can we set this to 1.8 V too`?
how?

Efuse for 1.8V is not set in factory, at least for now. If this is changed in the future, we will add a note to the datasheet.

Oh oops. SPI pin remap fuses are set but not vdd_sdio? Does that mean internal flash is connected to internal 1.8v ldo upstream of vdd_sdio pad? Or is it mandatory to operate in vdd_sdio = 1.8v even though fuse is not set?

h) if we combine ESP32-D2WD with ESP-pSRAM32 we must use 1.8V cause intern Flash and ESP-pSRAM32 share Dataline PINS

I'm not sure whether this is a supported combination — IIRC the internal flash uses some pins which we also use for CS & CLK for pSRAM.

Hmm well we still have 2 free pins in sdio domain unless something special about 16&17.

@wifi
i see a big problem in this :

if there comes wrover - and you forget to pullup bootstrap pin MTDI for VDD_SDIO - ( 3.3 - > 1.8 ) the pSRAM can be damaged ( 1.8 ).

the next question is then here, if we set this bootstrap pin MTDI example in WROOM-32 for VDD_SDIO 1.8
does this mean the CS PIN and Datapins are then 1.8V max too?.. can we set the pins by eFuse then to max 1.8 Voltage ?
each Pin or only SDIO Pins for SPI Flash ( SD0, SD1, SD2, SD3, SCS, SCLK )

cause the CS pin comes on high with 3.3V on the pSRAM in this if we must set difference from SPI Flash - example.

i think - i think to complex for this - i think we can set with eFuse the max Voltage on "each" pin - ( i hope so )
or how we manage then this with CLK and CS pins?

best wishes
rudi

[WiFive]

No, gpio 16&17 are in vdd_sdio domain that is why they were chosen for psram.

But yes it seems important to know about bootstrap requirements for wrover and d2wd.

[rudi ;-)]

No, gpio 16&17 are in vdd_sdio domain that is why they were chosen for psram.

But yes it seems important to know about bootstrap requirements for wrover and d2wd.

txs - so it can be, that 16, 17 is taken for CLK(1.8) and CS(1.8) in wrover example for pSRAM

yes - i see this too to know about bootstrap - a short try with a forget and zooom the pSRAM is damaged ..
- is there a reason not set eFuse on wrover and d2wd from espressif itself?
do we have later wrover / d2wd with a need 3.3 or 3.3V flash? i think no so why not eFuse this at production.



best wishes
rudi

[WiFive]

IMO the reason d2wd uses 16&17 for flash is because it was easier to wire bond between the two dies. So should be able to use 9&10 for psram with d2wd. But could be wrong.

[rudi ;-)]

ok - after some "cooked**" pSRAM and D2WD's i think i figured it out now - now is clear for see where the way must look for pSRAM and D2WD.

best wishes
rudi


**) i don't think they are damaged - but i would never take they again for testings.

[ESP_igrr]

Okay, can i finally give the reason why we don't burn the efuse for 1.8V in D2WD. The reason is, if the VDD_SDIO is configured by efuse, it takes some time for the hardware to read efuse values at startup. If the strapping pin configures VDD_SDIO to be 3.3V, then during this time, VDD_SDIO will be 3.3V. As soon as efuse read is complete, the regulator will switch to 1.8V.
So configuring 1.8V VDD_SDIO using Efuse is less robust than configuring 1.8V VDD_SDIO using a strapping pin. Some external circuitry could be used to overcome this limitation, but otherwise it is recommended to use strapping pin to set 1.8V SDIO voltage.
We will update the documentation to mention this.

With regards to using D2WD with PSRAM: it is possible, as the extra CS and CLK signals to PSRAM are routed via the GPIO matrix. But depending on the pins chosen, it may not be possible to achieve 80MHz clock due to timing differences between various pads. 40MHz clock should still be possible.