Unable write to I2C FIFO on ESP32C3

[zdmitriy]

Hi

I am developing driver for I2C nodule of EXP32C3 using tinygo and having issue writing to the FIFO register.
From the latest reference manual v0.5 it says 'In FIFO mode, the CPU writes to TX RAM via the fixed address I2C_DATA_REG, with addresses for writing in TX RAM incremented automatically by hardware.'
However, the documentation show that this register is read-only: 'I2C_FIFO_RDATA Data read from RX FIFO. (RO)', and no reference to TX FIFO.
Is this register in fact R/W or documentation missing the information for TX FIFO register?
Also, while I try to write into to I2C_DATA_REG register, I would expect the I2C_FIFO_ST_REG would reflect write position, but it is stay at 0 all the time.

Please advice.

Thanks
Dmitriy

[ESP_Sprite]

Yep, that looks like a mistake in the register description docs. I'll ping the documentation team to fix it.

Looking at the ll hal layer of the i2c driver in esp-idf, the data register indeed is writable, and sr.tx_fifo_cnt should indeed increase when you write that. Are you sure the I2C peripheral is un-clockgated and taken out of reset?

[zdmitriy]

Thank you for your reply!

I am new (or too old) to microcontrollers and may not understand all terminology.

I do set I2C_CLK_EN to 1, and I can see SCL signal when enable it in idle mode with analyzer. Is this what you meant by "un-clockgated"?
Not sure about reset. How do I check or take out of reset? I can't find anything related to this in the reference manual.
The status registers shows these values:
I2C_SR_REG: 0x3000c000 I2C_FIFO_ST_REG: 0x0 I2C_FIFO_CONF_REG: 0x708b

These are all the registers I am setting during initialization:

esp.SYSTEM.SetPERIP_CLK_EN0_EXT0_CLK_EN(1)
esp.I2C.SetCLK_CONF_SCLK_SEL(0) // use slow 0 for XTAL_CLK 40MHz, 1 for FOSC_CLK 17.5 MHz
clkmDiv := i2cSourceClk/config.Frequency + 1
esp.I2C.SetCLK_CONF_SCLK_DIV_NUM(clkmDiv)
esp.I2C.SetCLK_CONF_SCLK_ACTIVE(1)
esp.I2C.SetCTR_CLK_EN(1)

// init pins to input.output with PAD and Function 53/54

// init frequency
esp.I2C.SetSCL_LOW_PERIOD(sclLow - 1)
esp.I2C.SetSCL_HIGH_PERIOD(sclHigh)
esp.I2C.SetSCL_HIGH_PERIOD_SCL_WAIT_HIGH_PERIOD(sclWaitHigh)
esp.I2C.SetSCL_RSTART_SETUP_TIME(setup)
esp.I2C.SetSCL_STOP_SETUP_TIME(setup)
esp.I2C.SetSCL_START_HOLD_TIME(hold - 1)
esp.I2C.SetSCL_STOP_HOLD_TIME(hold - 1)
esp.I2C.SetSDA_SAMPLE_TIME(sda_sample)
esp.I2C.SetSDA_HOLD_TIME(sdaHold)

// enable master mode
esp.I2C.SetCTR_MS_MODE(1)
// enable SCL while idle
esp.I2C.SetSCL_SP_CONF_SCL_RST_SLV_EN(1)
esp.I2C.SetFIFO_CONF_NONFIFO_EN(0)
esp.I2C.SetFIFO_CONF_RX_FIFO_RST(1)
esp.I2C.SetFIFO_CONF_TX_FIFO_RST(1)
esp.I2C.SetCTR_CONF_UPGATE(1)

[ESP_Sprite]

You need to enable the peripheral by taking it out of reset and allowing it to get a clock signal. See table 14-2 (Clock Gating and Reset Bits) in the TRM.

[zdmitriy]

I see. I have missed the reset bit.
But even after added code to clear the reset bit (set and clear), it didn't make it work.
I got the same result: got SCL and no SDA.
PERIP_CLK_EN0: 0xf9c1e0ef PERIP_RST_EN0: 0x0

It seems something else is missing.
Is the order of initialization steps is critical?
I have PERIP_CLK_EN0 and PERIP_RST_EN0 done upfront during initialization.
Can RTC affect this?

PS: I have tested the board with esp-idf i2ctools and board works.

[zdmitriy]

I have some progress with FIFO.
Apparently I was not clearing RX_FIFO_RST and TX_FIFO_RST.
Now, I can see the FIFO address getting incremented with each write.
However, SDA is still silent and commands are not getting executed after I write 1 to I2C_TRANS_START.