ESP32-S3 DDR SPI

[bbranisalv99]

Looking at the ESP32-S3 datasheet
section 3.5.2 Serial Peripheral Interface (SPI), in the SPI2 General­purpose SPI (GP­SPI) mode part it's mentioned that SPI2 can do DDR at 40Mhz while in half duplex mode.

In the project i have a SPI slave chip that does DDR on the MISO line, as in MISO line needs to be sampled at both edges of the SCLK line. It's not a flash/ram chip, so I need to drive the SPI2 in the general purpose mode.

I wanted to confirm that this is what the datasheet says, but looking at API docs for ESP-IDF for ESP32-S3 only talks about SPI DDR for external flash modules.

Can someone clarify, can I use SPI2 in general purpose master mode with half duplex, to sample the MISO line on both edges of SCLK?

[ESP_Sprite]

It does have a DDR feature, but I don't think this feature is in the driver yet... Can you share what chip you're trying to communicate with? I can tell the driver team what to focus on if I file an issue to implement this.

[bbranisalv99]

The chip in question is RHD2164, you can see the DDR part on page 10 and 11

[chegewara]

@ESP_Sprite
Any update on this? Is DDR implemented yet?

[ESP_Sprite]

It is. Simply specify the flag SPI_DEVICE_DDRCLK.

[chegewara]

Thanks.

I am asking, because today i wanted to test it with my new devkit:
https://eu.mouser.com/ProductDetail/Esp ... cyCode=PLN

and here is result:

Code: Select all

rst:0x1 (POWERON),boot:0x18 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
Octal Flash Mode Enabled
For OPI Flash, Use Default Flash Boot Mode
mode:SLOW_RD, clock div:1
load:0x3fce3810,len:0x16a0
load:0x403c9700,len:0xbd0
load:0x403cc700,len:0x2c94
entry 0x403c9900
I (32) boot: ESP-IDF v5.1-dev-437-g5c1044d84d 2nd stage bootloader
I (32) boot: compile time 07:59:59
I (32) boot: chip revision: V001
I (35) boot_comm: chip revision: 1, min. bootloader chip revision: 0
I (42) boot.esp32s3: Boot SPI Speed : 80MHz
I (47) boot.esp32s3: SPI Mode       : SLOW READ
I (52) boot.esp32s3: SPI Flash Size : 32MB
I (57) boot: Enabling RNG early entropy source...
I (63) boot: Partition Table:
I (66) boot: ## Label            Usage          Type ST Offset   Length
I (74) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (81) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (88) boot:  2 factory          factory app      00 00 00010000 00100000
I (96) boot: End of partition table
I (100) boot_comm: chip revision: 1, min. application chip revision: 0
I (107) esp_image: segment 0: paddr=00010020 vaddr=3c090020 size=23418h (144408) map
I (150) esp_image: segment 1: paddr=00033440 vaddr=3fc98500 size=04f24h ( 20260) load
I (156) esp_image: segment 2: paddr=0003836c vaddr=40374000 size=07cach ( 31916) load
I (165) esp_image: segment 3: paddr=00040020 vaddr=42000020 size=80ecch (528076) map
I (291) esp_image: segment 4: paddr=000c0ef4 vaddr=4037bcac size=0c7b4h ( 51124) load
I (305) esp_image: segment 5: paddr=000cd6b0 vaddr=50000000 size=00010h (    16) load
I (314) boot: Loaded app from partition at offset 0x10000
I (314) boot: Disabling RNG early entropy source...
W (326) FLASH: DO NOT USE FOR MASS PRODUCTION! Timing parameters will be updated in future IDF version.
I (327) octal_psram: ECC is enabled
I (329) octal_psram: vendor id    : 0x0d (AP)
I (334) octal_psram: dev id       : 0x02 (generation 3)
I (340) octal_psram: density      : 0x03 (64 Mbit)
I (345) octal_psram: good-die     : 0x01 (Pass)
I (351) octal_psram: Latency      : 0x01 (Fixed)
I (356) octal_psram: VCC          : 0x00 (1.8V)
I (361) octal_psram: SRF          : 0x01 (Fast Refresh)
I (367) octal_psram: BurstType    : 0x00 ( Wrap)
I (372) octal_psram: BurstLen     : 0x03 (1024 Byte)
I (378) octal_psram: Readlatency  : 0x02 (10 cycles@Fixed)
I (384) octal_psram: DriveStrength: 0x00 (1/1)
W (389) PSRAM: DO NOT USE FOR MASS PRODUCTION! Timing parameters will be updated in future IDF version.
I (400) esp_psram: Found 8MB SPI RAM device
I (404) esp_psram: Speed: 80MHz
I (445) mmu_psram: Instructions copied and mapped to SPIRAM
I (457) mmu_psram: Read only data copied and mapped to SPIRAM

As you can see OPI is enabled, also i selected DTR in menuconfig, but SPI Mode is SLOW READ.
Here is sdkconfig.defaults:

Code: Select all

CONFIG_IDF_TARGET="esp32s3"
CONFIG_ESPTOOLPY_OCT_FLASH=y
CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
CONFIG_SPIRAM=y
CONFIG_SPIRAM_MODE_OCT=y
CONFIG_SPIRAM_TYPE_ESPPSRAM64=y
CONFIG_SPIRAM_IGNORE_NOTFOUND=y
CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y
CONFIG_SPIRAM_ECC_ENABLE=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
CONFIG_ESP32_WIFI_RX_BA_WIN=6
CONFIG_FREERTOS_HZ=1000

Thanks

[ESP_Sprite]

That is exactly the opposite of what OP asks (DDR for GSPI), suggest you start a new topic for this. One thing I do know is that we bring up octal stuff in fastread or slow-read mode in the bootloader and only switch to octal in the app code, that may be what you're seeing.

[Haiyunzx]

Have you achieved communication with RHD2164 with the ESP32 series chip? Is it available? @bbranisalv99@ESP_Sprite

[qwertyuio]

Hi, is there an update with the project? I'm trying to do the same intan headstage spi communication.