SPI in ESP32-S2R2

[harshpatel1307]

Hi Team,

We are a leading security system manufacturer in India and currently our system is running on ESP8266.

We have decided to develop new system using ESP32-S2 with PSRAM.

We have referred available datasheet but the following points are not clear to us:
1. Does flash and PSRAM using same SPI lines for data and clock ?
2. We need additional #2 SPI ports for other peripherals but we are not getting the SPI pins for user use (which is not used for flash and PSRAM)?

Further, please lets us know is there HW availablity issue with ESP32-S2-Solo for next 5 years.

Please review and share your inputs.
Thanks and regards
Patel

[ESP_LJH]

1. Yes, flash and PSRAM share same data and clock lines
2. You coud cofigure any available GPIO as other SPI lines
3. If it is possible, we suggest you to use updated module ESP32-S2-SOLO-2

[harshpatel1307]

Hi ESP_LJH

Thank you for the prompt response.
Your response provides the required information.

Regarding point #2, I need the following information:
As shown in attached snapshot of ESP32-S2 datasheet, GPIO 10,11,12,13 have SPI functionality and GPIO 34,35,36,37 have SPI functionality.
So are they different SPI ports or same SPI port is extended to other pins only?

Please let me know if any further information is required.
Thanks and regards,
Patel

[mvduin]

SPI on the ESP32-S2 can be somewhat confusing.

There are four SPI peripherals yet only three SPI buses, and each bus can support multiple slave devices using chip selects (up to 11 slaves total across the three buses):

SPI0 and SPI1 control the same spi bus, which uses the "SPI" prefix for its signal names (e.g. SPICLK). They are master-only and support two chip selects, reserved for flash (CS0) and psram (CS1). If I understand correctly, SPI0 is used for hardware-initiated transfers (memory-mapped flash read and psram read/write) while SPI1 is used by software-initiated transfers (e.g. flash programming).

SPI2 (aka GP-SPI2) uses the "FSPI" prefix for its signals (e.g. FSPICLK). It supports master and slave mode and has six chip selects (FSPICS0..5). It also has some signals and functionality specific to driving LCD panels.

SPI3 (aka GP-SPI3) uses the "SPI3_" prefix for its signals (e.g. SPI3_CLK). It supports master and slave mode and has three chip selects (SPI3_CS0..2). Unlike the other controllers it does not support quad/octal SPI, only traditional 1-bit SPI.

Any of these signals can be muxed to any GPIO via the GPIO Matrix. Additionally, the most important signals of SPI0/1 and SPI2 can also be muxed more directly to specific pins using IOMUX, which lacks the flexibility of the GPIO Matrix but presumably offers improved signal timing needed for the highest clock speeds (though I've not seen any actual timing specifications). Some signals of SPI2 have two mux options via IOMUX, which is what you highlighted in your comment. SPI3's signals can only be routed via the GPIO Matrix.

Here's an overview of all SPI signals of the ESP32-S2.

In conclusion, you can in fact have two separate independent buses (SPI2 and SPI3) if needed, in addition to the option of putting multiple (up to 6 for SPI2) slave devices on a single SPI bus.

(There are also occasional references to an "SPI4" peripheral and "SUBSPI" signals but I think this was something removed during design but never fully purged from documentation.)

[harshpatel1307]

Thank you for the detailed information. It answers my questions.

regards,
Patel