What is the state of I/O pins in reset?

[johnabel]

Hopefully a quick one, I couldn't find clearly in the specs: are all I/O pins in Hi-Z state when in reset?
And is reset pulling the CHIP_PU pin low? (DS says 'it works at minimum power', that doesn't imply a reset, does it? but there isn't any other rest related pin...)

[ESP_igrr]

Please check the "ESP32 Pin List" document (available from Espressif website). In the pin list table, see the two rightmost columns ("at reset", "after reset"). Notes 9 and 10 on the previous page explain the contents of these two columns

[johnabel]

I did, but for most of the GPIO those columns are blank. Note 9 says 'During reset, all pins are output-disabled' should I understand they are high-Z or weak pull up/down? And is RESET pulling CHIP_PU low?
Is, for example, GPIO25 an output after reset by default (because of the ie=0 at the last column)?

[ESP_igrr]

If the column is blank for a particular GPIO, then pullup, pulldown, and input are disabled (=hi-Z).
ie=0 means that input is disabled, but that doesn't mean the output is enabled, ie and oe settings are independent. All pins have outputs disabled at and after reset.

[johnabel]

Thanks, that makes sense now.
As input are usually high impedance, it doesn't make much sense to disable them, does it?
That's why I thought disabling them was actually a way of setting them to be outputs.
Anyways, I have now enough info to carry on.