The serial TX path seems to be down [custom board]

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gfurtadoalmeida
Posts: 5
Joined: Thu Oct 01, 2020 3:57 am

The serial TX path seems to be down [custom board]

Postby gfurtadoalmeida » Wed Jan 12, 2022 12:32 am

Hi,
I've designed a custom ESP32 board based on WROOM-32 module for home applications.
However, I am not able to flash it. The board can send data through UART (as shown below) but cannot receive the flash data.

When trying to flash, I get the following error:
Download mode successfully detected, but getting no sync reply: The serial TX path seems to be down.

The USB connection was copied from the esp32_devkitc_v4.
What could be wrong?

ESP-IDF version: ESP-IDF v4.4-dev-3235-g3e370c4296-dirty

Data sent by the board

Code: Select all

ets Jun  8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:8
load:0x3fff0010,len:3480
load:0x40078000,len:7804
ho 0 tail 12 room 4
load:0x40080000,len:252
entry 0x40080034
<ESC>[0;32mI (46) boot: ESP-IDF v2.0-3-gbef9896 2nd stage bootloader<ESC>[0m
<ESC>[0;32mI (47) boot: compile time 05:59:45<ESC>[0m
<ESC>[0;32mI (47) boot: Enabling RNG early entropy source...<ESC>[0m
<ESC>[0;32mI (66) boot: SPI Speed      : 40MHz<ESC>[0m
<ESC>[0;32mI (78) boot: SPI Mode       : DIO<ESC>[0m
<ESC>[0;32mI (91) boot: SPI Flash Size : 4MB<ESC>[0m
<ESC>[0;32mI (103) boot: Partition Table:<ESC>[0m
<ESC>[0;32mI (114) boot: ## Label            Usage          Type ST Offset   Length<ESC>[0m
<ESC>[0;32mI (137) boot:  0 phy_init         RF data          01 01 0000f000 00001000<ESC>[0m
<ESC>[0;32mI (160) boot:  1 otadata          OTA data         01 00 00010000 00002000<ESC>[0m
<ESC>[0;32mI (183) boot:  2 nvs              WiFi data        01 02 00012000 0000e000<ESC>[0m
<ESC>[0;32mI (207) boot:  3 at_customize     unknown          40 00 00020000 000e0000<ESC>[0m
<ESC>[0;32mI (230) boot:  4 ota_0            OTA app          00 10 00100000 00180000<ESC>[0m
<ESC>[0;32mI (253) boot:  5 ota_1            OTA app          00 11 00280000 00180000<ESC>[0m
<ESC>[0;32mI (277) boot: End of partition table<ESC>[0m
<ESC>[0;32mI (290) boot: Disabling RNG early entropy source...<ESC>[0m
<ESC>[0;32mI (307) boot: Loading app partition at offset 00100000<ESC>[0m
<ESC>[0;32mI (1482) boot: segment 0: paddr=0x00100018 vaddr=0x00000000 size=0x0ffe8 ( 65512) <ESC>[0m
<ESC>[0;32mI (1483) boot: segment 1: paddr=0x00110008 vaddr=0x3f400010 size=0x1c5f0 (116208) map<ESC>[0m
<ESC>[0;32mI (1499) boot: segment 2: paddr=0x0012c600 vaddr=0x3ffb0000 size=0x0215c (  8540) load<ESC>[0m
<ESC>[0;32mI (1529) boot: segment 3: paddr=0x0012e764 vaddr=0x40080000 size=0x00400 (  1024) load<ESC>[0m
<ESC>[0;32mI (1553) boot: segment 4: paddr=0x0012eb6c vaddr=0x40080400 size=0x1b028 (110632) load<ESC>[0m
<ESC>[0;32mI (1632) boot: segment 5: paddr=0x00149b9c vaddr=0x400c0000 size=0x00034 (    52) load<ESC>[0m
<ESC>[0;32mI (1633) boot: segment 6: paddr=0x00149bd8 vaddr=0x00000000 size=0x06430 ( 25648) <ESC>[0m
<ESC>[0;32mI (1649) boot: segment 7: paddr=0x00150010 vaddr=0x400d0018 size=0x7a56c (501100) map<ESC>[0m
<ESC>[0;32mI (1676) heap_alloc_caps: Initializing. RAM available for dynamic allocation:<ESC>[0m
<ESC>[0;32mI (1699) heap_alloc_caps: At 3FFBA6B8 len 00025948 (150 KiB): DRAM<ESC>[0m
<ESC>[0;32mI (1720) heap_alloc_caps: At 3FFE8000 len 00018000 (96 KiB): D/IRAM<ESC>[0m
<ESC>[0;32mI (1741) heap_alloc_caps: At 4009B428 len 00004BD8 (18 KiB): IRAM<ESC>[0m
<ESC>[0;32mI (1762) cpu_start: Pro cpu up.<ESC>[0m
<ESC>[0;32mI (1774) cpu_start: Single core mode<ESC>[0m
<ESC>[0;32mI (1787) cpu_start: Pro cpu start user code<ESC>[0m
<ESC>[0;32mI (1848) cpu_start: Starting scheduler on PRO CPU.<ESC>[0m
<ESC>[0;32mI (2017) uart: queue free spaces: 10<ESC>[0m
Bin version:0.10.0<CR>
I (2018) wifi: wifi firmware version: c604573
I (2018) wifi: config NVS flash: enabled
I (2019) wifi: config nano formating: disabled
I (2027) wifi: Init dynamic tx buffer num: 32
I (2028) wifi: wifi driver task: 3ffc4f34, prio:23, stack:3584
I (2033) wifi: Init static rx buffer num: 10
I (2037) wifi: Init dynamic rx buffer num: 0
I (2041) wifi: Init rx ampdu len mblock:7
I (2045) wifi: Init lldesc rx ampdu entry mblock:4
I (2050) wifi: wifi power manager task: 0x3ffca2dc prio: 21 stack: 2560
I (2056) wifi: wifi timer task: 3ffcb35c, prio:22, stack:3584
<ESC>[0;31mE (2061) phy_init: PHY data partition validated<ESC>[0m
<ESC>[0;32mI (2084) phy: phy_version: 329, Feb 22 2017, 15:58:07, 0, 0<ESC>[0m
I (2084) wifi: mode : softAP (7c:9e:bd:39:c6:c1)
I (2087) wifi: mode : sta (7c:9e:bd:39:c6:c0) + softAP (7c:9e:bd:39:c6:c1)
I (2091) wifi: mode : softAP (7c:9e:bd:39:c6:c1)
Schematic.jpg
Schematic.jpg (257.04 KiB) Viewed 11648 times
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ESP_Sprite
Posts: 9769
Joined: Thu Nov 26, 2015 4:08 am

Re: The serial TX path seems to be down [custom board]

Postby ESP_Sprite » Wed Jan 12, 2022 1:10 am

Your schematic looks reasonable. Could it be that there is something wrong with the trace labeled CPU_RX0 in your schematic; could you double-check the solder joints and maybe even put an oscilloscope on that pad of the ESP32 module to see if it's active on that side?

EDIT: Also, I would make C34 larger; the datasheet advises 1uF, but you could even try 10uF.
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gfurtadoalmeida
Posts: 5
Joined: Thu Oct 01, 2020 3:57 am

Re: The serial TX path seems to be down [custom board]

Postby gfurtadoalmeida » Sat Jan 15, 2022 8:49 pm

ESP_Sprite, indeed, the problem was the solder joints on the QFN package.
The project was changed to add the 1uF capacitor that you (and the datasheet) suggested.
Thank you very much!
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ESP_Sprite
Posts: 9769
Joined: Thu Nov 26, 2015 4:08 am

Re: The serial TX path seems to be down [custom board]

Postby ESP_Sprite » Sun Jan 16, 2022 1:25 am

Glad you could make it work!
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