Paging memory on a larger flash chip

[dovoto]

We have a need for more memory mapped flash and are looking at the following:

Use a larger NOR flash chip (W25Q256/512 or similar)in 24 bit addressing mode (its default) and use custom commands to change the extended address byte register to page in memory, clear the cache and go about our marry way.

Is it possible to send custom commands like this (for this specific chip: 0xC5 xx where xx is the high byte of the address)?

We have also thought about using two 16MB flash chips on the bus and gating the CS lines (at the cost of another used IO and some external logic).

[chegewara]

How about S2 or S3 which both support up to 1GB(1Gb) flash according to datasheet and support up to 64MB will be added soon in esp-idf?