external interrupt jitter

[FL0WL0W]

I did some more digging into the IDF

It looks like RTOS is setting up the interrupts without setting the level. Then in esp_intr_alloc_intrstatus, it is being defaulted to ESP_INTR_FLAG_LOWMED which could potentially assign it a level 3 interrupt.

However, I changed it to default to Level 1 interrupt, but the issue still persists, so it is not necessarily a interrupt level issue. So it is probably some critical section of the IDF that is blocking interrupts and causing a pretty significant delay. This is unfortunate as it makes it unusable for my use case.

I will have to explore disabling IDF on Core 1 and making my app run on it. This also brings up another question, if IDF enters a critical section on core 0, will it also disable interrupts on core 1? Also, will the gpio, intterupts, and hardware timer functions still work with IDF disabled on Core 1? I don't want to have to rewrite them.

[ESP_Sprite]

However, I changed it to default to Level 1 interrupt, but the issue still persists, so it is not necessarily a interrupt level issue.

Note that level 1 is the level with the *least* priority. Higher levels = higher priority in Xtensa. I'm not surprised this doesn't do anything.

I will have to explore disabling IDF on Core 1 and making my app run on it. This also brings up another question, if IDF enters a critical section on core 0, will it also disable interrupts on core 1? Also, will the gpio, intterupts, and hardware timer functions still work with IDF disabled on Core 1? I don't want to have to rewrite them.

Yes, but do note that disabling IDF on core 1 (in menuconfig) simply does not run anything on that core. There are ways to get core 1 entirely to yourself, but these mostly are about running FreeRTOS on both cores, then disabling the FreeRTOS tick timer interrupt on core 1. There's some examples on the forum for that.

[FL0WL0W]

However, I changed it to default to Level 1 interrupt, but the issue still persists, so it is not necessarily a interrupt level issue.

Note that level 1 is the level with the *least* priority. Higher levels = higher priority in Xtensa. I'm not surprised this doesn't do anything.

Yes i know, i set all of the rtos interrupts to level1, and the gpio interrupt to level 3. this did not help because there are alot of critical sections in the rtos that disable interrupts.

Is there any information on running raw on the core 1? I just need to know how to get core 1 to run app_main and i can take it from there

[FL0WL0W]

Any way to enable CONFIG_FREERTOS_UNICORE without it also forcing CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE? That way i can implement my own esp_startup_start_app_other_cores function.

[xwwang051]

hi friend
Do you have resloved the problem of external interrupt jitter? I have the same problem now .
Looking forward to your reply! thanks!

[FL0WL0W]

I was able to implement AMP (Asymmetric Multi-Processing) and get core 1 to run my own bare metal applications. After installing the ISR service to run on core 1, I was able to reduce the interrupt jitter down to 1us.

My PR can be found here. https://github.com/espressif/esp-idf/pull/12800