Needed additional pins for PSRAM

[q2222ch]

Hello,
I'm working on a board where I would like to be ready to use PSRAM in the future. In the table 3-1. "ESP-WROVER-KIT Description" in the document "ESP-WROVER-KIT Getting Started Guide" Link, in chapter 3, it is mentioned that GPIO16 and GPIO17 are used as the CS and clock signal for PSRAM.

Is this information still valid?- In practice- as I understand it- this would mean that the two devices on the "SPI" bus (system SPI bus as I call it), the "system SPI flash" and the future PSRAM are sharing the "SPI" data lines however each of the two devices has its own clock signal (pin no. 31 for the flash, pin no. 27 for the PSRAM). In addition pin no. 25 of the ESP32 would be used as dedicated CS signal for the PSRAM beside the defined CS for the SPI flash on pin no. 30.

Are I missing something or is my understanding correct?

Another point: Does the internal 1.8V LDO supply enough power for the SPI flash and the PSRAM or do I have do use an external 1.8V supply?

Or simply asked: Within which timeframe can we expect the release of the ESP32-WROVER module schematics that would answer all my above questions?

Thank you for the answers.

[ESP_Sprite]

Yes, that information about GPIO16/17 is still true. Afaik the hardware we run here runs the PSRAM off the internal LDO; I haven't seen an external 1.8V LDO on our boards.

[q2222ch]

OK, thank you very much for the answer. It is unbelievable how fast you replied: Hats off!

[q2222ch]

Excuse my additional silly question:
However after thinking of it I could not find a technically satisfying answer. Why are you really using a 1.8V VDD_SDIO supply on the ESP32-WROVER module (based on the photos that can be found on the Internet)? Is it just because the supplier of the PSRAM devices can only deliver the chips with the 1.8V supply voltage at the moment and the 3.3V version of the chips will start sampling not before middle of 2017?

Thank you.

[colman]

Is it possible to share the PSRAM's clock with SPI Flash clock on pin 31, just like sharing the data lines; so that only one extra pin is required for the PSRAM chip select?

Colman

[ESP_Sprite]

No, sorry. The flash and psram have slightly different timing requirements, and the intrinsics of the cache mechanism makes it impossible to cater to both using one clock line. I was surprised by that myself as well and suggested a few workarounds to the digital team, but seems they already thought of all of them and the only way to make it work is by using a separate clock line.

[q2222ch]

Would it be possible to further clarify the planned/ realized usage of the pins GPIO16, GPIO17?- In my first post I added the link to the document "ESP-WROVER-KIT Getting Started Guide" where it is mentioned - in chapter 3- that GPIO16 and GPIO17 are used as the CS and clock signals for the PSRAM. In the newer documents, for example in the datasheet V1.3 in chapter "2.0 pin definitions" it can be found in the first note below the table (on page 9): "ESP32D2WD’s pins GPIO16, GPIO17, SD_CMD, SD_CLK, SD_DATA_0 and SD_DATA_1 are used for connecting the embedded flash, and are not recommended for other uses". Is this really correct?

Or asked the other way round:
In the devices ESP32D0WD and ESP32D0WDQ6 the CS and the clock pins for the flash (external) are SD_CMD (pin 30) and SD_CLK (pin 31). => the QSPI interface for the flash consists of the pins 30, 31, 32, 33, 28 and 29. In addition based on the timing the additional pins 25 and 27 are used for the CS and clock functionality of an optional PSRAM.

What is going on in the device ESP32D2WD? Based on the note below the table in the datasheet the flash interface uses other pins. => the QSPI interface seems to use the pins 25, 27, 30, 31, 32 and 33. based on the documentation the pins 28 and 29 (SD_DATA_2, SD_DATA_3) are "free" not used for the QSPI. Is this really correct?

Thank you for the clarification.

[ESP_igrr]

In D2WD, the flash chip is connected internally to GPIOs 6 (clk), 7(wp), 8(d), 11(hd), 16(cs), 17(q). This is pre-configured using SPICONFIG_ block of fields in the EFUSE.

[q2222ch]

OK, thank you very much for your answer. If I understand it correctly based on the documentation this means (as a consequence) that the internal flash in the device ESP32-D2WD is connected via GPIO Matrix not directly through the IO_MUX. Is my interpretation of the documentation right?

[WiFive]

And as a followup is internal flash limited to 40mhz?