ESP32-S3 (Beta2) MARLIN_9_1B on ESP32-S3-Addax-1 V1.0 Specs & Datasheet

[rudi ;-)]

There is a esp32-s3 technical reference manual ?

not public yet - but there is one.
in the meanwhile few info is available in part of code. furher parts : S2part S3part further ( there are many hints in the code)

Hi,

It looks like they're not using spi octal bus.

And it looks like both flash memory and external ram memory share the same sqi bus.

They should have made a chip that supported independent sqi bus access to each memory (flash and external ram).

yeap - this modul not using spi octal bus - i have few OPI samples (APMemory, ISSI, .. ) here ( Flash and PSRAM ) in 200 Mbps and 133 Mbps Datarate version ( 1.8V / 3.3 V ) - i think i will use in final design the 1.8V version ( flash and psram ) perhabs 256Mb flash and 256Mb psram in the base, and 1Gb in a test, cause they are fast enough ...

btw:

**easter egg in the IDF**
note 1: MX25UM25645G Octa Flash

ISSI PSRAM 256Mb ( Mouser: 870-6WVOM38DAL200BLI Manufacturer: IS66WVO32M8DALL-200BLI )
APmemory PSRAM 64Mb further


Preview:
i will update this post on weekend with a "dark pixeld" OPI Version Modul so you can not traceroute the traces on modul
but by code - i think now i will be killed by you then if i did this let me think over few days how i can do it.


best wishes
rudi


EDIT
...OPI Version...

easter egg

MX25UM25645G-OPI.png (225.23 KiB) Viewed 28371 times

EDIT2
**further easter egg in the IDF**
GigaDevice GD25LX256E Flash (Octa Flash Datasheet )
DigiKey 1970-GD25LX256EBIRY-ND

[neggles]

Hi @neggles,

I was basing my assumptions on the esp32-s2 chip technical reference manual, but esp32-s3 may have a different dma architecture.

"This is new, I think? DMA access to external RAM was not previously possible, as far as I can tell"
In esp32-s2 thecnical reference manual this is possible too.

ESP32-S2 has three types of DMA, namely Internal DMA, EDMA and Copy DMA. Internal DMA can only access
internal RAM and is used for data transfer between internal RAM and peripherals. EDMA can access both
internal RAM and external RAM and is used for data transfer between internal RAM, external RAM and
peripherals. Copy DMA can only access internal RAM and is used for data transfer from one location in internal
RAM to another.

Regarding the communication with the flash memory and external ram memory, i would be very happy with a sqi ddr bus for each memory, with independent cache/memory controller for each external memory.

Totally fair, I'm just going off the ESP32-S3 datasheet which certainly isn't as detailed. We can only hope, I suppose?

...OPI Version...

Awesome! Dual octal-SPI! *ahem* CALLED IT!

[Baldhead]

Hi @rudi,

Very cool octal spi for flash and ram memory.

Only 3 questions about octal flash and octal psram memory:

1) The price of these two memories(flash and psram) are at a very high price, most likely each memory costs more than the esp32-s3.

2) Current consumption it seemed a little high. I don't know if it may or may not be a problem.

3) The esp32-s3 octal bus is ddr, sdr or both ?

[rudi ;-)]

3) The esp32-s3 octal bus is ddr, sdr or both ?

if you read the preview linked codelines to the esp-idf and these opi-flash header and spi-flash headers, you will see, that the the ESP-IDF is little behind the R&D / Marketing ...or ... the R&D / Marketing is little ahead - but you find the needed answeres between the lines for S2 in the meantime where TRM is not up2date or S3 not public / pre-released yet.

ESP32-S3
ESP32-S2


only to complete the things:

ESP32
ESP32-C3

ESP32-C6
-not yet sry-
edit 2021-Sept-19 (append ESP32-C6 from Announcing )

ESP32-C6-Announcing

ESP32-C6-Announcing_April_2021.png (126.63 KiB) Viewed 19283 times

In 1 + 2 there are no questions
not only the price for flash/ram is now near doubled last time by problems in few suppliers - it is general happens last weeks with semiconductors - the octal is more usefull as the Q/D version and all is dependent on the usecase's also dependent on the need- if ones need octal flash/ram it needs more power too sure, the new octal series 1.8V ( 200 ) are not bad in the current consumption, there are few things also from winbond with 1.2V - which was talked here in the BBS in past too.
also have a note to this company BOYAMICRO. They have the 256M ( or here ) also the 512 as SOIC-8 and they named it with 5µA in the 32'ish Datasheet and use dtr. BY25Q32* it is used with the ESP32-C6 in the Testboard. BY delivery also KGD for SiP / MCP.

btw:
the mentioned Marketing case is mean to the NEW ESP32-C6_Test_Board V1.0 with SMA Conn. (PIC attached, SMA cutted ) likewise the ESP8266 launcher has - C6 was spotted in the wild last hour's ... there is no "C6" in the ESP-IDF ./.not have been discovered.. yet

ups.. C6 is named here now too
( new thread is need )

[Baldhead]

Hi @rudi,

This winbond seems interesting:
https://www.winbond.com/hq/product/mobi ... Mb#Density

And here my sugestion:
viewtopic.php?t=2772&start=390
Hi,

A solution similar to this one looks interesting for a wrover board, especially for the esp32-s3 chip.

Flash memory and ram memory in a single package with one shared dtr octal spi bus interface.

OR

Flash memory and ram memory in a single package with two dtr sqi bus interface.

https://www.prnewswire.com/news-release ... 56587.html

HyperRam, HyperFlash and HyperRam + HyperFlash in a single package.
https://www.cypress.com/search/psg/117351

[Baldhead]

Hi @rudi,

Do you know if hardware dma descriptor in new devices will change the limit from 12 bits in size and in lenght ?

Somewhere around 24 or even 32 bits would be very interesting.

Thank's.

[rudi ;-)]

Flash memory and ram memory in a single package with one shared dtr octal spi bus interface.
OR
Flash memory and ram memory in a single package with two dtr sqi bus interface.
HyperRam, HyperFlash and HyperRam + HyperFlash in a single package.

Yeap - MCP all here at Workbench Desk, also a not oficial patch for ESP-IDF code is ready
i am waiting for few R&D groups inside and between them clearing things,
also you should know, that ESP-IDF currently only supports Espressif branded PSRAM chips (ESP-PSRAM32, ESP-PSRAM64, etc).
so far - i think there comes few new things - and is in the (not oficial) pipe
( i can not share pics cause i do not want show them now until few deskwork is final )
see meanwhile the Octal RAM version of the new ESP32-S3 ( MARLIN_9_1B ) Wrover Modul wit APS64..

Do you know if hardware dma descriptor in new devices will change the limit from 12 bits in size and in lenght ?
Somewhere around 24 or even 32 bits would be very interesting.

just's
ESP32
ESP32-S2
ESP32-S3
ESP32-C3
new
ESP32-C6 not yet public in the Repo

24, 32 bits .. purely out of my curiosity in demand, what would you do with it DMA HW ?

the lldesc_t technic is nice, the ( lldesc_s ) next desc. buffer's you can make by your request by self you know?

[Baldhead]

Hi @rudi,

Another sugestion:
Esp32-s3 with internal chip memory like "ESP32-PICO-V3-02".

Maybe with more memory.
Maybe octal ddr.

[Baldhead]

Hi @rudi,

"so far - i think there comes few new things - and is in the (not oficial) pipe"

Yes, i just suggested some nice ideas. I think that espressif can manufacture these memories too.

"24, 32 bits .. purely out of my curiosity in demand, what would you do with it DMA HW ?"

Lcd display driver.

"the lldesc_t technic is nice, the ( lldesc_s ) next desc. buffer's you can make by your request by self you know?"

Yes, i already use it, but i need calculate how many lldesc_s i need to use every time I'm going to send a partial frame with variable size to the display.
With a bigger size / length I didn’t will need to calculate and would still save processing time and some ram memory.

[Baldhead]

Hi @rudi,

Another suggestions to put inside a new espressif chip:

* lcd controller hardware module, maybe with mipi dsi support and other comum interfaces support too.

* dma2d like some stm32 for 2d rendering acceleration.

* maybe a 2d gpu