Inconsistent MISO data on SPI.

[Talesduque]

Hello everyone, im using SPI to communicate my FPGA to my ESP32, i'm currently sending a stream of decimal numbers (all 33, 16bit transaction), sometimes the data isnt registered correctly, as shown in the screenhot. Seems like the MISO line is not completely stable (?). I'm gonna post my code and the screenshot I'm talking about!

Erro.png (96.77 KiB) Viewed 2914 times

erro2.png (37.63 KiB) Viewed 2911 times

Code: Select all

extern "C" void spi_task(void *pvParameters)
{      
    spi_transaction_t t;
    esp_err_t ret;
    int16_t k = 0;
    uint16_t sendbuf[64] = {0};
    uint16_t recvbuf[64] = {0};
    uint16_t valorreal;
    uint16_t aux2 = 0;
    long start = 0;
    long stop = 0;
    memset(recvbuf, 122, 128);
    memset(&t, 0, sizeof(t));
    t.length= sizeof(sendbuf)*8;
    t.rxlength = sizeof(recvbuf)*8;
    t.rx_buffer=recvbuf;
    t.tx_buffer = NULL;
    gpio_set_level(GPIO_ERROR,1); // Sincronizar na inicialização o envio do FPGA
    uint16_t aux;
    printf("spi_task rodando no core: ");
    printf("%u\n",xPortGetCoreID());
    while(1) 
    {
        memset(recvbuf, 122, 128);
        xSemaphoreTake(rdySem, portMAX_DELAY); //Wait until slave is ready
        ret=spi_device_transmit(handle, &t);
        transf++;
        start = xTaskGetTickCount();
        for(int i = 0; i<64; i++ )
        {
            aux = recvbuf[i]; // Inserindo dados recebidos na fila
            xQueueSend(xQueue, &aux, portMAX_DELAY);
        }
        stop  = ((xTaskGetTickCount()-start)*portTICK_PERIOD_MS);
    }
}

Code: Select all

spi_bus_config_t buscfg={
        .mosi_io_num=GPIO_MOSI,
        .miso_io_num=GPIO_MISO,
        .sclk_io_num=GPIO_SCLK,
        .quadwp_io_num=-1,
        .quadhd_io_num=-1
    };

    spi_device_interface_config_t devcfg={
        .command_bits=0,
        .address_bits=0,
        .dummy_bits=0,
        .mode=0,
        .duty_cycle_pos=128, 
        .cs_ena_pretrans=10,
        .cs_ena_posttrans=10, //Keep the CS low 3 cycles after transaction, to stop slave from missing the last bit when CS has less propagation delay than CLK
        .clock_speed_hz=5000000,
        .input_delay_ns=10,
        .spics_io_num=GPIO_CS,    
        .flags = SPI_DEVICE_NO_DUMMY,
        .queue_size=1
    };

    //Configuration for the handshake line
    gpio_config_t io_conf={
        .pin_bit_mask=(1<<GPIO_HANDSHAKE),
        .mode=GPIO_MODE_INPUT,
        .pull_up_en= GPIO_PULLUP_ENABLE,
        .intr_type=GPIO_INTR_POSEDGE,
    };

Anyone know why that is happening? Thanks!

[chegewara]

What logic analyzer and what sampling rate do you use?

[Talesduque]

I'm using Logic16 with 40MS/s.

I'm also using the following pins

Code: Select all

#define GPIO_MOSI (gpio_num_t)12
#define GPIO_MISO (gpio_num_t)13
#define GPIO_SCLK (gpio_num_t)15
#define GPIO_CS (gpio_num_t)14

[Talesduque]

It seems like that is only showing on the logic analyzer, the ESP actually receives the right data.

I've added the following code

Code: Select all

xQueueReceive(xQueue, &queuerecv, portMAX_DELAY);
                    queuerecv = ((queuerecv << 8) | (queuerecv >> 8));
                    buffercirc(queuerecv);
                    if(queuerecv != 33)
                    {
                        printf("It's wrong. \n");
                    }