U4WDH are all the Dn Pins used for internal flash?

[Scott.Bonomi]

Looking at the Data lines reserved for internal U4WDH flash memory, I do not see any signals on D0, D2 or D3. I see a 40 Mhx clock on the CLK Line, And I see a 3V data signal on D1. Is D1 the only data line being used under normal operation? Under all operations?
I am looking for another GPIO or two and do not want to use the JTAG pins until no other choice.

[ESP_igrr]

Quoting the ESP32 datasheet:

The pin-pin mapping between ESP32-D2WD/ESP32-U4WDH and the embedded flash is as follows: GPIO16 = CS#, GPIO17 = IO1/DO, SD_CMD = IO3/HOLD#, SD_CLK = CLK, SD_DATA_0 = IO2/WP#, SD_DATA_1 = IO0/DI. The pins used for embedded flash are not recommended for other uses.

So GPIO16, GPIO17, CMD, CLK, D0, D1 pins are used. Since the default mode is "DIO", you will not see any activity on D0 and CMD (which are WP and HOLD of Flash). If you switch flash mode to QIO in menuconfig, then these pins will also get used.
Note that even if you configure the application to use DIO mode, D0 and CMD are still connected to the flash chip's WP and HOLD, which means that you can't run arbitrary signals through those pins.

[Scott.Bonomi]

I agree that the document says that but I was hoping it was more boilerplate than fact. I was not aware that the flash mode for internal could be changed, nice to know.
Thank You
- - Scott