Boot strapping pins and power-on reset

[colman]

According to the ESP32 datasheet, the latching of the strapping pins is done during chip power-on reset and these bits are held until the chip is powered down or shut down. But in my experiment, the level on these strapping pins also affect the boot mode during RTCWDT_RTC_RESET. In my design, I have to connect a EMAC physical to ESP32, since at this moment the only possible configuration is using the external 50MHz input from GPIO0, I used a tristate buffer to disconnect the RMII clock to GPIO0 when CHIP_PU pin is low and turn the buffer on at a time 100mS after CHIP_PU is high. At the first time, it will boot from SPI FLASH, but after a RTCWDT_RTC_RESET, it will boot from UART1 download. It seems that these strapping pin is sampled whenever the CPU is reset, not only at the CHIP_PU pin rising, is it true?

Regards,
Colman

[ESP_Sprite]

Yes, unfortunately it is, which makes connecting the clock to GPIO0 slightly hard... for the next chip, we will make sure that we won't have any input signals that are not movable to another pin connected to a bootstrap pin anymore.

For now, our internal solution is to use another GPIO pin as a 'clock-enable' output: only by making that pin active-high, GPIO0 will receive the clo0ck output from the PHY.

[WiFive]

for the next chip, we will make sure that we won't have any input signals that are not movable to another pin connected to a bootstrap pin anymore.

May as well go to 56 or 64 pins too