ESP Ethernet custome boards going to fail in FCC

[yagnik.pokal]

Hi,

I have developed the ESP32 custom board with an ethernet interface. I used the LAN8720 PHY chip with ESP32. Taken a reference from olimax ethernet board.
The board works fine but it was going to fail in FCC. As per my knowledge on my board, the only ethernet is operated at 50 Mhz. The configuration I used is IO0 as a clock output with an inverter buffer. I have added a schematics screenshot here. I changed the series resistor. but it doesn't work.

You can see in the 50mhz screenshot that at every 50mhz interval EMI/EMC is failing. Should I miss somewhere here?

[ESP_Angus]

Hi yagnik,

You're right that unwanted 50MHz harmonics are probably something to do with the ethernet layout, and most likely the clock.

I noticed that there is no termination on the EMAC_CLK transmission line, where it is driven by the buffer. This is probably the first place I would look, especially if this trace has any length at all. Other than that, the problem may be to do with aspects of the board layout rather than the schematic design.

If you're not familiar with high speed digital design for EMC compliance then you may need to either do some quick study, or engage a consultant. The good news is that the design only seems to be failing marginally, so it should be easy enough to make it pass.

[yagnik.pokal]

Hi yagnik,

You're right that unwanted 50 MHz harmonics are probably something to do with the Ethernet layout, and most likely the clock.

I noticed that there is no termination on the E MAC_CLK transmission line, where it is driven by the buffer. This is probably the first place I would look, especially if this trace has any length at all. Other than that, the problem may be to do with aspects of the board layout rather than the schematic design.

If you're not familiar with high speed digital design for EMC compliance then you may need to either do some quick study, or engage a consultant. The good news is that the design only seems to be failing marginally, so it should be easy enough to make it pass.

Thanks for sharing the information.
I have created a new version for my board and added a series termination resistor.See the series resistor image.

Apart from that i have also changed the layout. I have added old layout screen shot and new layout screen shot with length matching on clock and data line. See attached files.

I have keep all the dateline like RXD0, RXD1, TXD0, TXD1, EMACK_CLK as short as possible. this time i have given a good ground plane for clock and dateline. I have given 1.5X separation for clock line to any other symbol or any other track. As it is fail marginally this time it will pass.

Still in a attachment if you feel any problem let me know. Thanks for your support it will help me a lot.

[mikemoy]

yagnik, I know it way late for this but if you cant get it sorted out you may want to try this.
viewtopic.php?f=17&t=5479&start=30#p55405

You can dump U9 and its supported components, and make it much simpler.

[ESP_Angus]

Hi yagnik,

It's hard to say for sure from the images, and this is a bit beyond the support we normally provide on this forum. For the record, It is possible to request specific hardware support, but for a custom design like this it would be a paid service. Note that it doesn't seem like the problem here is ESP32-specific, so another consulting EE or PCB designer could also give you feedback.

There is also the possibility that the clock trace is not the problem, and it's something to do with the PHY itself or some other connections to the PHY.

However, it sounds like the changes you've made are a measurable improvement on the original design, so I think you have a good reason to expect everything will pass the second time around! Best of luck.

Angus

[yagnik.pokal]

Hi yagnik,

It's hard to say for sure from the images, and this is a bit beyond the support we normally provide on this forum. For the record, It is possible to request specific hardware support, but for a custom design like this it would be a paid service. Note that it doesn't seem like the problem here is ESP32-specific, so another consulting EE or PCB designer could also give you feedback.

There is also the possibility that the clock trace is not the problem, and it's something to do with the PHY itself or some other connections to the PHY.

However, it sounds like the changes you've made are a measurable improvement on the original design, so I think you have a good reason to expect everything will pass the second time around! Best of luck.

Angus

Sounds good for my solution. Thanks

[yagnik.pokal]

yagnik, I know it way late for this but if you cant get it sorted out you may want to try this.
viewtopic.php?f=17&t=5479&start=30#p55405

You can dump U9 and its supported components, and make it much simpler.

Yes you are right, I have added the XTAL footprint in my board. It will help me if i fail with U9 buffer. It helps a lot. Thank you.