Transparent Wi-Fi module with RMII input
Re: Transparent Wi-Fi module with RMII input
hi
Are there progresses?
best wishes
rudi
Are there progresses?
best wishes
rudi
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Re: Transparent Wi-Fi module with RMII input
Working on it. We have a prototype here that mostly works, needs some polishing and then we'll have a final version that we can sell.
Re: Transparent Wi-Fi module with RMII input
ah.. you have a working model? fine!ESP_Sprite wrote:.. that we can sell.
can i ask on which ETH PHY silicon? ( tlk110 ? )
can you say how you create the clk for RMII ( 50 MHz )
do you use
Code: Select all
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT)
https://github.com/espressif/esp-idf/issues/345
or other technical, extra osz?
PoE very welcome -ESP_Sprite wrote:..The reference design includes PoE as well,....I'll see if I can post the schematics.
jeroen, we need for our hw a solution on GPIO16 with silicon v0
is it possible or must we wait for silicon v1
in testings have generated clk with spi 40 MHz, with I2S 37MHz
how we can generate a 50 MHz APLL for use on FUNC_GPIO16_EMAC_CLK_OUT ?
best wishes
rudi
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love it, change it or leave it.
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Re: Transparent Wi-Fi module with RMII input
Rudi, as I was working on clock related stuff, I got the recipe to enable 50MHz clock for you:
Sorry, no idea whether that works with EMAC (there may be more settings needed to make EMAC actually use this clock), but at least it gets 50MHz out of IO16. Hope this helps.
Edit: rtc_plla_ena function signature may change, this function may be removed, you may get eaten by raptors if you use it, etc, etc.
Code: Select all
extern void rtc_plla_ena(bool ena, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
// for rev0 chip: f_out = f_xtal * (sdm2 + 4) / (2 * (o_div + 2))
// so for 40MHz XTAL, sdm2 = 1 and o_div = 1 will give 50MHz output
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
REG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_H_DIV_NUM, 0);
REG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_DIV_NUM, 0);
REG_CLR_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_EXT_OSC_EN);
REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_INT_OSC_EN);
rtc_plla_ena(1, 0, 0, 1, 0);
Edit: rtc_plla_ena function signature may change, this function may be removed, you may get eaten by raptors if you use it, etc, etc.
Re: Transparent Wi-Fi module with RMII input
Ivan,
i am on the road just in time i will test asap.. asap my friend next 3 hour*s
will test all and let you know asap
big thank you!
best wishes
rudi
i am on the road just in time i will test asap.. asap my friend next 3 hour*s
will test all and let you know asap
big thank you!
best wishes
rudi
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love it, change it or leave it.
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問候飛出去的朋友遍全球魯迪
love it, change it or leave it.
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Re: Transparent Wi-Fi module with RMII input
hi ivan
short and dirty, get the 50/51MHz,
edit: see next post, the 50/51 comes from echo line by Rmii board with 50MHz osc on board.
now need to be filter, sharper ..
the rest i will test next few hours.
thank you ivan!
best wishes
rudi
short and dirty, get the 50/51MHz,
edit: see next post, the 50/51 comes from echo line by Rmii board with 50MHz osc on board.
now need to be filter, sharper ..
the rest i will test next few hours.
thank you ivan!
best wishes
rudi
- Attachments
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- 50MHz_Clk.jpg (182.58 KiB) Viewed 16736 times
Last edited by rudi ;-) on Tue Feb 28, 2017 6:35 pm, edited 1 time in total.
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love it, change it or leave it.
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Re: Transparent Wi-Fi module with RMII input
ups,
my early shot i must take back:
hi ivan,
Had measured the loop with 50 MHz RMII on the module on the meter
And received the 50 therefore and with Jitter ..
Now I have only the esp32 on osz and try a few settings
But I always get only 40 MHz.
usually 40
40 MHz * (0 + 4 ) / ( 2 * (0 + 2 ) = 40 MHz
but get 40 MHz
usually 50
40 MHz * (1 + 4 ) / ( 2 * (0 + 2 ) = 50 MHz
but get 40 MHz
usually 60 theoretical
40 MHz * (2 + 4 ) / ( 2 * (0 + 2 ) = 60 MHz
but get 40 MHz
best wishes
rudi
my early shot i must take back:
hi ivan,
Had measured the loop with 50 MHz RMII on the module on the meter
And received the 50 therefore and with Jitter ..
Now I have only the esp32 on osz and try a few settings
But I always get only 40 MHz.
usually 40
40 MHz * (0 + 4 ) / ( 2 * (0 + 2 ) = 40 MHz
Code: Select all
rtc_plla_ena(1, 0, 0, 0, 0);
usually 50
40 MHz * (1 + 4 ) / ( 2 * (0 + 2 ) = 50 MHz
Code: Select all
rtc_plla_ena(1, 0, 0, 1, 0);
usually 60 theoretical
40 MHz * (2 + 4 ) / ( 2 * (0 + 2 ) = 60 MHz
Code: Select all
rtc_plla_ena(1, 0, 0, 2, 0);
best wishes
rudi
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love it, change it or leave it.
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問候飛出去的朋友遍全球魯迪
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Re: Transparent Wi-Fi module with RMII input
bingo
50 MHz
figured it out
50 MHz
figured it out
Last edited by rudi ;-) on Tue Feb 28, 2017 7:24 pm, edited 1 time in total.
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love it, change it or leave it.
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Re: Transparent Wi-Fi module with RMII input
btw: 139MHz
thank you
when we get technical docu about rtc_plla_ena
its in the new librtc_clk.a
btw, there a small parameter idx mistake in the given pvParameter
but have figured it out - now we try to push to RMII clock as referer
best wishes
rudi
156 MHz ( 160 MHz )
@ivanthank you
when we get technical docu about rtc_plla_ena
its in the new librtc_clk.a
and rtc_plla_ena is not described at time
rtc_clk.o rtc_xtal_32k_ena
rtc_clk.o rtc_8m_ena
rtc_clk.o rtc_plla_ena
rtc_clk.o rtc_set_slow_freq
rtc_clk.o rtc_set_fast_freq
rtc_clk.o rtc_bbpll_md
rtc_clk.o rtc_init_xtal_freq
rtc_clk.o rtc_get_xtal
rtc_clk.o rtc_apb_freq_up
rtc_clk.o rtc_uart_div_modify
rtc_clk.o rtc_uart_tx_wait_idle
rtc_clk.o rtc_set_cpu_freq
rtc_clk.o rtc_init_clk
rtc_clk.o rtc_init_clk_lite
btw, there a small parameter idx mistake in the given pvParameter
but have figured it out - now we try to push to RMII clock as referer
best wishes
rudi
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love it, change it or leave it.
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問候飛出去的朋友遍全球魯迪
love it, change it or leave it.
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問候飛出去的朋友遍全球魯迪
Re: Transparent Wi-Fi module with RMII input
What is the correction?rudi ;-) wrote:
btw, there a small parameter idx mistake in the given pvParameter
but have figured it out
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