Transparent Wi-Fi module with RMII input

[rudi ;-)]

hi
Are there progresses?

best wishes
rudi

[ESP_Sprite]

Working on it. We have a prototype here that mostly works, needs some polishing and then we'll have a final version that we can sell.

[rudi ;-)]

.. that we can sell.

ah.. you have a working model? fine!
can i ask on which ETH PHY silicon? ( tlk110 ? )

can you say how you create the clk for RMII ( 50 MHz )
do you use

Code: Select all

PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT)

https://github.com/espressif/esp-idf/issues/345

or other technical, extra osz?

..The reference design includes PoE as well,....I'll see if I can post the schematics.

PoE very welcome -

jeroen, we need for our hw a solution on GPIO16 with silicon v0
is it possible or must we wait for silicon v1

in testings have generated clk with spi 40 MHz, with I2S 37MHz

how we can generate a 50 MHz APLL for use on FUNC_GPIO16_EMAC_CLK_OUT ?

best wishes
rudi

[ESP_igrr]

Rudi, as I was working on clock related stuff, I got the recipe to enable 50MHz clock for you:

Code: Select all

    extern void rtc_plla_ena(bool ena, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
    // for rev0 chip: f_out = f_xtal * (sdm2 + 4) / (2 * (o_div + 2))
    // so for 40MHz XTAL, sdm2 = 1 and o_div = 1 will give 50MHz output

    PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
    REG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_H_DIV_NUM, 0);
    REG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_DIV_NUM, 0);
    REG_CLR_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_EXT_OSC_EN);
    REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_INT_OSC_EN);
    rtc_plla_ena(1, 0, 0, 1, 0);

Sorry, no idea whether that works with EMAC (there may be more settings needed to make EMAC actually use this clock), but at least it gets 50MHz out of IO16. Hope this helps.


Edit: rtc_plla_ena function signature may change, this function may be removed, you may get eaten by raptors if you use it, etc, etc.

[rudi ;-)]

Ivan,
i am on the road just in time i will test asap.. asap my friend next 3 hour*s
will test all and let you know asap

big thank you!

best wishes
rudi

[rudi ;-)]

hi ivan
short and dirty, get the 50/51MHz,

edit: see next post, the 50/51 comes from echo line by Rmii board with 50MHz osc on board.

now need to be filter, sharper ..
the rest i will test next few hours.

thank you ivan!
best wishes

rudi

[rudi ;-)]

ups,
my early shot i must take back:


hi ivan,

Had measured the loop with 50 MHz RMII on the module on the meter
And received the 50 therefore and with Jitter ..

Now I have only the esp32 on osz and try a few settings
But I always get only 40 MHz.

usually 40
40 MHz * (0 + 4 ) / ( 2 * (0 + 2 ) = 40 MHz

Code: Select all

rtc_plla_ena(1, 0, 0, 0, 0);  

but get 40 MHz

usually 50
40 MHz * (1 + 4 ) / ( 2 * (0 + 2 ) = 50 MHz

Code: Select all

rtc_plla_ena(1, 0, 0, 1, 0); 

but get 40 MHz

usually 60 theoretical
40 MHz * (2 + 4 ) / ( 2 * (0 + 2 ) = 60 MHz

Code: Select all

rtc_plla_ena(1, 0, 0, 2, 0);  

but get 40 MHz

40MHz.jpg (133.66 KiB) Viewed 16814 times

best wishes
rudi

[rudi ;-)]

bingo

50 MHz

50Mhz_glass_clear.jpg (137.7 KiB) Viewed 16812 times

figured it out

[rudi ;-)]

btw: 139MHz

139MHz_glassClear.jpg (128.31 KiB) Viewed 16803 times

156 MHz ( 160 MHz )

156MHz.jpg (126.86 KiB) Viewed 16803 times

@ivan
thank you
when we get technical docu about rtc_plla_ena
its in the new librtc_clk.a

rtc_clk.o rtc_xtal_32k_ena
rtc_clk.o rtc_8m_ena
rtc_clk.o rtc_plla_ena
rtc_clk.o rtc_set_slow_freq
rtc_clk.o rtc_set_fast_freq
rtc_clk.o rtc_bbpll_md
rtc_clk.o rtc_init_xtal_freq
rtc_clk.o rtc_get_xtal
rtc_clk.o rtc_apb_freq_up
rtc_clk.o rtc_uart_div_modify
rtc_clk.o rtc_uart_tx_wait_idle
rtc_clk.o rtc_set_cpu_freq
rtc_clk.o rtc_init_clk
rtc_clk.o rtc_init_clk_lite

and rtc_plla_ena is not described at time

btw, there a small parameter idx mistake in the given pvParameter
but have figured it out - now we try to push to RMII clock as referer



best wishes
rudi

[WiFive]

btw, there a small parameter idx mistake in the given pvParameter
but have figured it out

What is the correction?