SUMP Compatible ESP32 Logic Analyzer with RLE
SUMP Compatible ESP32 Logic Analyzer with RLE
Hello.
I just published my code on github.
It's ESP32 Logic Analyzer which is SUMP compatible 16Bit captures up to 20Mhz using I2S DMA.
I am able to see 20 Mbps UART communication with it using PulseView/Sigrok.
Unfortunately my device is not WROOVER one which has much more RAM on it.
If you not willing to send me one, current code has only capture up to 128K sample using 256Kbyte of memory for buffer.
Well it does NOT support analog input.
Project page: https://github.com/EUA/ESP32_LogicAnalyzer
I just published my code on github.
It's ESP32 Logic Analyzer which is SUMP compatible 16Bit captures up to 20Mhz using I2S DMA.
I am able to see 20 Mbps UART communication with it using PulseView/Sigrok.
Unfortunately my device is not WROOVER one which has much more RAM on it.
If you not willing to send me one, current code has only capture up to 128K sample using 256Kbyte of memory for buffer.
Well it does NOT support analog input.
Project page: https://github.com/EUA/ESP32_LogicAnalyzer
Last edited by E.U.A. on Fri Mar 06, 2020 2:38 pm, edited 1 time in total.
Admin of the SamyGO.tv, Samsung TV Hacking Project
Re: SUMP Compatible ESP32 Logic Analyzer
Hi E.U.A., this is an awesome project!
If you send me a PM with your postal address and phone number, we'll send you a development kit with a WROVER module and Ethernet.
If you send me a PM with your postal address and phone number, we'll send you a development kit with a WROVER module and Ethernet.
Re: SUMP Compatible ESP32 Logic Analyzer
Ah thank you!
Than I will use extra ram buffer to expand sampling on it.
I will send PM about it.
I am little sad about sampling speed which is limited to 20Msps.
I found that If I use QSPI interface, I can sample up to 80Msps 4bit but I am not sure if it supports such a long RX reception.
But found that Arduino-esp32 don't support QSPI DMA, yet.
Otherwise I plan to use Dual QSPI with DMA to archive 80Msps 8Bit device implementation.
If I found such a some sample, will try to implement it also.
Thanks!
Than I will use extra ram buffer to expand sampling on it.
I will send PM about it.
I am little sad about sampling speed which is limited to 20Msps.
I found that If I use QSPI interface, I can sample up to 80Msps 4bit but I am not sure if it supports such a long RX reception.
But found that Arduino-esp32 don't support QSPI DMA, yet.
Otherwise I plan to use Dual QSPI with DMA to archive 80Msps 8Bit device implementation.
If I found such a some sample, will try to implement it also.
Thanks!
Admin of the SamyGO.tv, Samsung TV Hacking Project
Re: SUMP Compatible ESP32 Logic Analyzer
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Re: SUMP Compatible ESP32 Logic Analyzer
Excellent work!
You must be sampling faster than 20Mhz to see a 20Mbps uart...
You must be sampling faster than 20Mhz to see a 20Mbps uart...
E.U.A. wrote: ↑Wed Feb 05, 2020 2:35 amHello.
I just published my code on github.
It's ESP32 Logic Analyzer which is SUMP compatible 16Bit captures up to 20Mhz using I2S DMA.
I am able to see 20 Mbps UART communication with it using PulseView/Sigrok.
Unfortunately my device is not WROOVER one which has much more RAM on it.
If you not willing to send me one, current code has only capture up to 128K sample using 256Kbyte of memory for buffer.
Well it does NOT support analog input.
Project page: https://github.com/EUA/ESP32_LogicAnalyzer
Re: SUMP Compatible ESP32 Logic Analyzer
Thank you.mikronauts wrote: ↑Wed Feb 05, 2020 8:53 pmExcellent work!
You must be sampling faster than 20Mhz to see a 20Mbps uart...
Yes, If you are working on analog signals, you are correct. You need sample at least 4 times faster than signal you gonna analyze for proper sampling.
But if you are gonna sample digital signals... Nope. You can sample at (exactly) same speed.
If two sampling clocks are exactly in same speed, they will be synchronized and you can analyze/capture the transmission.
But if there is a slight de synchronization, result is not looks like what you expect.
Since I sampling using DMA and clock generated by ESP32's hardware and is exactly 20Mhz (and minimal jitter on it), I could read precise 20Mbaud digital transmissions. And ESP8266 send TX burst via Hardware (again, no jitter and in exact 20Mhz clock), viola!
At top, 10Mbaud signal, at bottom 20Msps one. On 20Msps UART signal, there are some minor errors on stopbits section but transmission captured value is correct.
And here is the ESP8266 code which I generate signal from,
DIY and see if you could.
- #include "sigma_delta.h"
- #include <ESP8266WiFi.h>
- #include <ArduinoOTA.h>
- #include <WiFiManager.h>
- const char* host_name = "esp8266-TestSignal";
- //#define SignalBaud 2304000 // 2M baud!
- //#define SignalBaud 4000000 // 4M baud!
- //#define SignalBaud 4608000 // 4M baud!
- //#define SignalBaud 8000000 // 8M baud!
- #define SignalBaud1 10000000 // 10M baud!
- //#define SignalBaud 16000000 // 16M baud!
- #define SignalBaud2 20000000 // 10M baud!
- #define SignalFreq 1000000 //1M
- //#define SignalFreq 2000000 //2M
- //#define SignalFreq 10000000 //10M
- //#define SignalFreq 20000000 //20M
- byte xbyte;
- void setup() {
- Serial.begin(115200);
- Serial1.begin(SignalBaud1);// 8M baud!
- Serial.println("\r\n\r\n\r\n");
- Serial.println("ESP8266 TestSignal");
- Serial.println("Connecting...");
- WiFi.mode(WIFI_STA);
- WiFiManager wifiManager;
- wifiManager.setConfigPortalTimeout(600);
- if (!wifiManager.autoConnect()) {
- Serial.println("failed to connect and hit timeout");
- //reset and try again.
- ESP.reset();
- delay(1000);
- }
- WiFi.hostname( host_name );
- WiFi.setSleepMode( WIFI_LIGHT_SLEEP );
- Serial.println("");
- Serial.println("WiFi connected");
- Serial.println("IP address: ");
- Serial.println(WiFi.localIP());
- ArduinoOTA.setHostname(host_name);
- ArduinoOTA.begin();
- //Serial.println("Turn of built in LED.");
- //digitalWrite(BUILTIN_LED, HIGH);//Turn off led
- pinMode(4, OUTPUT);
- uint32_t SigmaDeltaPin = D6;
- int prescaler = 8;
- int SigmaDeltaChannel = 0;
- int freq = sigmaDeltaSetup(0, SignalFreq);
- prescaler = 80000000/SignalFreq;
- sigmaDeltaAttachPin(SigmaDeltaPin); // D6
- //sigmaDeltaWrite(SigmaDeltaChannel, 1);
- sigmaDeltaWrite(SigmaDeltaChannel, 125);
- sigmaDeltaSetPrescaler(prescaler); // 80Mhz / prescaler
- Serial.printf("\n\n\nSigmaDelta PWM working on port D6 with Freq of %0.2f Mhz\r\n", SignalFreq/1000000.0);
- Serial.println("Starting Test signal on Serial1 (D4)");
- Serial.println("Setting GPIO4 HIGH while sending.");
- Serial.printf("SignalBaud from Serial1 TXD using %d baud\r\n", SignalBaud1 );
- Serial.printf("SignalBaud from Serial TXD using %d baud\r\n", SignalBaud2 );
- Serial.println("Closing terminal.");
- Serial.flush();
- Serial.end();
- xbyte=0;
- Serial.begin(SignalBaud2);
- }
- uint32_t w=0;
- void loop() {
- if((w++%100)==0) //To reduce wait between samples.
- ArduinoOTA.handle();
- digitalWrite(4, HIGH );
- Serial1.write(xbyte);
- Serial.write(xbyte++);
- digitalWrite(4, LOW );
- }
Admin of the SamyGO.tv, Samsung TV Hacking Project
- jgustavoam
- Posts: 164
- Joined: Thu Feb 01, 2018 2:43 pm
- Location: Belo Horizonte , Brazil
- Contact:
Re: SUMP Compatible ESP32 Logic Analyzer
Congratulations EUA !
I and my friend Rui Viana are studying to develop the same project!
And you won! I will test your project and then post my results.
I made one recent progress - I set I2S master clock up to 80 MHz (tested) ! Awesome.
I2S BCK is derived from the master clock.
viewtopic.php?f=18&p=55305#p55305
Thanks a lot!
Gustavo Murta
I and my friend Rui Viana are studying to develop the same project!
And you won! I will test your project and then post my results.
I made one recent progress - I set I2S master clock up to 80 MHz (tested) ! Awesome.
I2S BCK is derived from the master clock.
viewtopic.php?f=18&p=55305#p55305
Thanks a lot!
Gustavo Murta
Last edited by jgustavoam on Sun Feb 09, 2020 4:07 pm, edited 1 time in total.
Retired IBM Brasil
Electronic hobbyist since 1976.
Electronic hobbyist since 1976.
Re: SUMP Compatible ESP32 Logic Analyzer
While I am working on real-time (20Mhz) RLE encoder code...
I want to ask something,
for
I expect I2S DMA samples in order of 00 s1 00 s2, 00 s3 00 s4, ...
But when I reach the dma buffer via pointer, and read it byte by byte, It looks like: 00 s2 00 s1, 00 s4 00 s3, ...
Why?
Does it related with endianess?
I coded as dma element union as:
As you see, first, sample 2 at top. But I expect it need to be like:
Well, it doesn't so big problem but I am racing with clocks and I just have 12 clock to encode each sample...
If there are some quick fix for that, I will be happy.
Thanks.
I want to ask something,
for
Code: Select all
I2S0.fifo_conf.rx_fifo_mod = 1;// SM_0A0B_0C0D = 1,
But when I reach the dma buffer via pointer, and read it byte by byte, It looks like: 00 s2 00 s1, 00 s4 00 s3, ...
Why?
Does it related with endianess?
I coded as dma element union as:
Code: Select all
typedef union {
struct {
uint8_t sample2;
uint8_t unused2;
uint8_t sample1;
uint8_t unused1;
};
struct{
uint16_t val2;
uint16_t val1;
};
uint32_t val;
} dma_elem_t;
Code: Select all
uint8_t unused1;
uint8_t sample1;
uint8_t unused2;
uint8_t sample2;
If there are some quick fix for that, I will be happy.
Thanks.
Last edited by E.U.A. on Sun Feb 09, 2020 5:00 pm, edited 1 time in total.
Admin of the SamyGO.tv, Samsung TV Hacking Project
- jgustavoam
- Posts: 164
- Joined: Thu Feb 01, 2018 2:43 pm
- Location: Belo Horizonte , Brazil
- Contact:
Re: SUMP Compatible ESP32 Logic Analyzer
Hi EUA,
Did you see this code ?
esp32-camera/driver/camera.c
https://github.com/espressif/esp32-came ... r/camera.c
https://github.com/espressif/esp32-came ... a_common.h
How FIFO sends or receives Bytes?
Did you see this code ?
esp32-camera/driver/camera.c
https://github.com/espressif/esp32-came ... r/camera.c
https://github.com/espressif/esp32-came ... a_common.h
How FIFO sends or receives Bytes?
Code: Select all
typedef enum {
/* camera sends byte sequence: s1, s2, s3, s4, ...
* fifo receives: 00 s1 00 s2, 00 s2 00 s3, 00 s3 00 s4, ...
*/
SM_0A0B_0B0C = 0,
/* camera sends byte sequence: s1, s2, s3, s4, ...
* fifo receives: 00 s1 00 s2, 00 s3 00 s4, ...
*/
SM_0A0B_0C0D = 1,
/* camera sends byte sequence: s1, s2, s3, s4, ...
* fifo receives: 00 s1 00 00, 00 s2 00 00, 00 s3 00 00, ...
*/
SM_0A00_0B00 = 3,
} i2s_sampling_mode_t;
Retired IBM Brasil
Electronic hobbyist since 1976.
Electronic hobbyist since 1976.
Re: SUMP Compatible ESP32 Logic Analyzer
Hi jgustavoam,
It's possible to clock I2S up to 80Mhz but the point is, does it support SLAVE mode?
Since we are reading (RX) from I2S, ESP32 expect external clock not use internal derived one.
I pass this requirement via feeding a pin via generated external clock signal and routing to I2S clk pin. But after 20Mhz, it doesn't work proper.
If there is a way to make I2S slave mode using internal clock, I easy implement it to code and support up to 80, or at least 40Mhz...
It's possible to clock I2S up to 80Mhz but the point is, does it support SLAVE mode?
Since we are reading (RX) from I2S, ESP32 expect external clock not use internal derived one.
I pass this requirement via feeding a pin via generated external clock signal and routing to I2S clk pin. But after 20Mhz, it doesn't work proper.
If there is a way to make I2S slave mode using internal clock, I easy implement it to code and support up to 80, or at least 40Mhz...
jgustavoam wrote: ↑Sun Feb 09, 2020 4:04 pmCongratulations EUA !
I and my friend Rui Viana are studying to develop the same project!
And you won! I will test your project and then post my results.
I made one recent progress - I set I2S master clock up to 80 MHz (tested) ! Awesome.
I2S BCK is derived from the master clock.
viewtopic.php?f=18&p=55305#p55305
Thanks a lot!
Gustavo Murta
Admin of the SamyGO.tv, Samsung TV Hacking Project
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