UART driver low level detals and false break detect

[drmacro]

Is there anyone here who has detailed knowledge of the inner workings of the uart driver?

Any guru's about?

I am having problems receiving a 512 byte broadcast.

It returns a break detect status after 480 bytes (it is receiving them 120 at a time). It does receive the first 360 bytes, but at that point the break detect is received and there are and additional 120 bytes in the receive buffer and another 32 bytes should arrive before the next break. (This is confirmed by watching the serial stream on a logic analyzer.)

There is a define in the uart.c:

Code: Select all

#define UART_FULL_THRESH_DEFAULT (120)

I'm guessing this is why the driver is returning 120 at a time. But, I can't see anything that would indicate why there would be a false break detect.

[drmacro]

The best I can tell the following is going on.

after the break detect, it reads 120 bytes for each UART_DATA event.
(i.e. the event is triggered when the fifo gets to 120 chars.)
because after 480, it only sees 32 bytes.
these bytes are never read, because the 120 threshold is never hit; event not triggered
so the, next break detect comes along
I think when the break is detected, the buffer is cleared (though I can't find where it does this in uart.c), but, event.size is never changed (it still says 120)
so, attempting to read 120 (or just 32) bytes fails.

so the question is: how to get the remaining bytes before the break detect happens.

[drmacro]

This is now an issue in github:

https://github.com/espressif/esp-idf/issues/4537