ESP-WROOM-32: Quad SPI Chip Selects

[BrettG]

Hi, I have a quick question about the Quad SPI Busses on the ESP-WROOM-32.

I saw on the datasheet that there are 3 chip selects available for both HSPI and VSPI when running as General Purpose SPI, but if we are running in Quad Spi configuration there seems to be only one Chip select available.

Is this true, if we want to use Quad SPI we are only allowed one Chip select per SPI Bus?

Also, just making sure the SPI1 Bus is reserved only for writing to the serial flash. No other peripherals may be connected to it, correct?

Thanks for your help.
- Brett

[ESP_Sprite]

Where do you see this? The TRM makes no such reference, at least not to what I recall.

SPI1 at the moment in esp-idf can indeed only be used for writing to flash. We want to update the SPI driver to also allow access to other devices connected via a different CS pin, but that's not in the driver yet.

[BrettG]

It is not said directly in either the datasheet or the docs, but I am referring to the esp_wroom_32 datasheet, section 3.5: Peripheral Interface Description.

Here is a snip of the section I am talking about:

3_5_SPI.PNG (202.19 KiB) Viewed 12689 times

From what I gather from that section, there is only one CS for each Parallel QSPI: VSPICS0, HSPICS0, SPICS0

- Brett

[ESP_Sprite]

I think that may be misleading. As far as I can see, every device connected to one of the three CS pins of a SPI host can be in single-wire or dual or quad mode.

[BrettG]

That is good to hear. What document are you getting this from?

[ESP_Sprite]

The TRM, mostly. The way the SPI registers are built strongly hint at QIO etc being a per-transaction thing you can enable on any CS.