Need to enable and disable all interrupts

[ashigupta9]

Hi,

Is there any specific function available that can be use to disable all interrupts in both cores and enable all interrupts?

Regards,
AG

[ESP_Sprite]

What would you need that for?

[ashigupta9]

I wanted this to create a critical section where execution should not switch once it has entered in that particular section.

[ESP_Sprite]

And what would you need *that* for? (Asking because we may have an xy problem here.)

[Aussie Susan]

Don't be too hard on the OP.
Stopping interrupts is a common way to make a series of non-atomic operations 'atomic'.
For example (not necessarily from the ESP32 world) - reading a 32-bit value from 2 16-bit registers. In some cases the hardware will expect this and copy the top 16-bits to a special place when you read the bottom 16 bits but there are many situations where you have to do this type of thing.
On other devices, if there is a 'register unlock' sequence, then you must not allow the consecutive instructions to be interrupted.
Or if you want to do floating point operations is an ISR but you could be interrupting another floating point operation where the hardware does not save these registers. (Not saying this is a good thing to do, but it can explain why you don't want an interrupt occurring in the middle of a code sequence.
I've no idea what the OP is trying to do but there can be situations why this is a reasonable thing to do.
Susan

[ESP_Sprite]

I'm not trying to be hard on OP, I just want to have him put the actual problem here, to save everyone lots of frustration. For instance, in this case, it would be the *wrong* way to do atomics, but I couldn't tell him that unless I knew he was trying to do that. That's why I want to know the entire problem.

[ashigupta9]

And what would you need *that* for? (Asking because we may have an xy problem here.)

I believe there are multiple reasons where someone wants to disable all interrupts when some critical section is getting executed.
In my case particularly, i want to have a RAM test at startup and i would not want to any context switch during that execution.
Hence disabling all CPU 0 and 1 interrupts for that duration are required.

[PeterR]

And the cache if PSRAM
Best to explain your use case to get the fullest answer.

Does anyone test onchip RAM? There are no pins to be loose so would not a failure be catastrophic & so cause wider issues?

[ESP_Sprite]

That's a good point. Do you only want to test external RAM or also internal RAM? External RAM already is / can be tested on startup (I think it's a menuconfig option that's on by default, if not it's just always on), for internal RAM you probably want to insert your RAM testing code before core 1 or the RTOS is up in order to be able to test as much memory possible.