Allocate 2 buffers in specific address at different memory banks

[ESP_Angus]

In "esp32_technical_reference_manual_en.pdf", page 307, says:
When TX_LEN is less than I2S_TX_DATA_NUM[5:0], the transmitted data, which is buffered in FIFO, has not reached the set threshold and
software can continue feeding data into FIFO.
- How does the dma controller know when tx fifo is full ?
- is it automatic or do i need to set something (maybe interrupt) ???

This section only applies if you don't use DMA and choose to fill the FIFO from software. In other words, this is automatic if using DMA.

In "esp32_technical_reference_manual_en.pdf", page 119, says:
However, unlike the SPI DMA channels, the data size for a single transfer is one word, or four bytes.

* My data buffer are of type uint16_t.
* The i2s lcd mode are 8 bits parallel.
* The dma data size for a single transfer is one word, or four bytes( uint32_t ).
* The data read/write packet length for a FIFO operation is 32 bits.

If i want to write only one byte or a number of bytes that are not multiple of 4 bytes ?

This is a two stage process. DMA will fill the TX FIFO of the I2S peripheral, then I2S peripheral reads the data from the FIFO to write to the LCD.

The DMA stage (or even writing directly into the FIFO from CPU) has restrictions on transfer size. The I2S peripheral will read data from the FIFO based on its configuration, see section "12.4.4 Sending Data" plus the additional "LCD" modes.

[Baldhead]

Hi ESP_Angus,

"This is a two stage process. DMA will fill the TX FIFO of the I2S peripheral, then I2S peripheral reads the data from the FIFO to write to the LCD."
I already understood that.

"The DMA stage (or even writing directly into the FIFO from CPU) has restrictions on transfer size. The I2S peripheral will read data from the FIFO based on its configuration, see section "12.4.4 Sending Data" plus the additional "LCD" modes."
I already read these section. The problem is that i didn't understand that part(12.4.4 Sending Data).


Thank's.

[Baldhead]

Hi,

In "esp32_technical_reference_manual_en.pdf", page 119, says:
However, unlike the SPI DMA channels, the data size for a single transfer is one word, or four bytes.

* My data buffer are of type uint16_t.
* The i2s lcd mode are 8 bits parallel.
* The dma data size for a single transfer is one word, or four bytes( uint32_t ).
* The data read/write packet length for a FIFO operation is 32 bits.
* The dma descriptor are in byte size.

If i want to write only one byte or a number of bytes that are not multiple of 4 bytes ?


I think that i need configure these register in a correct way:
* I2S_TX_FIFO_MOD[2:0]
* I2S_TX_CHAN_MOD[2:0]
* I2S_TX_MSB_RIGHT
* I2S_TX_BITS_MOD
* I2S_TX_RIGHT_FIRST
* I2S_TX_MSB_SHIFT

Can you show me how to configure these registers ?

Thank's.

[Baldhead]

Hi,

What are these magic numbers that don't appear in the esp32 documentation ?

#define I2S0_FIFO_ADD 0x6000f000
#define I2S1_FIFO_ADD 0x6002d000

In esp-idf i dont enconter these register too "I2S_FIFO_WR_REG" in file "i2s_struct.h".

I need to write like this ?
WRITE_PERI_REG( 0x3FF4F000, (uint8_t) value );

in "soc.h"
//write value to register
#define WRITE_PERI_REG(addr, val) ({ \
ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
})


Thank's.

[Baldhead]

Or,

REG_WRITE( 0x3FF4F000, (uint8_t) value );

[Baldhead]

Hi ESP_Angus,

"I'd suggest getting to a point where your new driver works, and see if the performance is good enough even with possible bus contention. If you see that you really need this at that point, we can probably find a way for you to make it work."

My i2s parallel driver now it's looking like it's working(without interrupt and without 2 buffers sync yet). I'm doing step by step.

At first my driver was already working for a while.
The problem i was not understanding that i could not write byte by byte directly in the i2s module with dma/output port.

In the function:
"https://github.com/espressif/esp-iot-so ... lcd.c#L336", the uint8_t function parameter buffer need to be copied to a uint32_t buffer ( using only 25% of uint32_t buffer capacity ).

There is a way to configure the i2s module with dma so that i don't need to copy a buffer from uint8_t to a buffer from uint32_t ?
Is this a bug in the i2s with dma module that was poorly designed ?

The memory waste is too big and there is also the cpu time to copy the buffer.

I would like to directly pass a uint8_t or uint16_t buffer to the i2s module with dma without need another buffer(uint32_t) to copy and spend so much memory.


Thank's for the help.

[Baldhead]

Hi,

Someone from espressif please.

I already submitted a technical inquiries.

How long to respond to the technical inquirie ?

Thank's.

[ESP_Angus]

Hi,

What are these magic numbers that don't appear in the esp32 documentation ?

#define I2S0_FIFO_ADD 0x6000f000
#define I2S1_FIFO_ADD 0x6002d000

In esp-idf i dont enconter these register too "I2S_FIFO_WR_REG" in file "i2s_struct.h".

These are AHB equivalents of the I2S_FIFO_WR_REG register for I2S0 and I2S1 which are shown in the TRM.

Most ESP32 peripherals are mapped to two buses, DPORT and AHB. so the same register can appear at two addresses. In almost all cases, it's preferable to use the DPORT address range (0x3ff.....) as performance is better. For write FIFO operations only (ie when data is written to the same address multiple times), using the AHB bus address is better.

For example, IDF header uart_reg.h includes a separate FIFO address register definition for the UART write FIFO on both AHB & DPORT buses.

IDF doesn't seem to include any definitions for the I2S FIFO, probably because the IDF I2S driver doesn't include a FIFO mode. Will raise a ticket internally to get these added. Seems they are used in the LCD driver, I'm guessing that's where you found them.

I need to write like this ?
WRITE_PERI_REG( 0x3FF4F000, (uint8_t) value );

This is how to write to a register address, but normally wouldn't recommend hardcoding a register address instead of using a macro.

[ESP_Angus]

My i2s parallel driver now it's looking like it's working(without interrupt and without 2 buffers sync yet). I'm doing step by step.

Great to hear.

In the function:
"https://github.com/espressif/esp-iot-so ... lcd.c#L336", the uint8_t function parameter buffer need to be copied to a uint32_t buffer ( using only 25% of uint32_t buffer capacity ).

There is a way to configure the i2s module with dma so that i don't need to copy a buffer from uint8_t to a buffer from uint32_t ?
Is this a bug in the i2s with dma module that was poorly designed ?

I'll check, but I think this is the only way when using DMA and 8 bits per transfer.

[Baldhead]

Hi,

"I'll check, but i think this is the only way when using DMA and 8 bits per transfer."
I will be anxiously waiting by the answer.
I hope there is a way to transfer an 8 bit buffer directly, because with a 32 bit buffer there is a lot of memory waste.

/////////////////////////////////////////////////////////////////////////////////////////////////////////////

I made some suggestions for a future chip at this link: "viewtopic.php?f=2&t=2772&start=310".

* configurable parallel port(with data/command, chip select, reset, write/read, all configurable ) in isolation from the i2s module.
A parallel port module just for that, i believe that it would simplify the existing i2s module(if espressif want to change it) and simplify user programmability.
* mipi dsi module.
* graphical controller(with tearing support).
* independent communication with psram and flash memory(dual sqi controller maybe, more package pin 64 pins maybe), so on boot i can load a critical part of flash into psram memory and during "normal operation" there would be no bus stall between psram/flash read/write. May be one cache for flash and one cache for psram if possible. Mapped memory.
* Someone from Espressif commented that sram memory occupies a lot of space on the chip. Stacked memory maybe(has the cost issue). MAIX-I wifi version have 8MB internal sram at low cost. "https://www.indiegogo.com/projects/sipe ... -ai-module#/".
* 64 pin package.
* A system on a module (SOM) like wrover b modules.
* more internal static ram/cache.
* powerfull fpu/dsp instructions.
* FreeRtos support for static allocation memory.
* +1 proper documentation(hardware documentation is poor, more software/hardware examples).

And i'm sorry if i was rude somehow.

Thank's.