Reading ADC using I2S

[szmodz]

I'm having problems getting ADC pattern tables to work correctly with I2S DMA. The problems seem to be somehow related to APB_SARADC_MAX_MEAS_NUM in APB_SARADC_CTRL2_REG, which is not documented.

I've posted about this on github:
https://github.com/espressif/esp-idf/pull/1991

Sampling works, but the channel sequence is messed up. I've developed a potential fix by trial and error, but can't verify that it's actually correct.

Can somebody from Espressif take a look and explain:

1. How to properly configure the I2S peripheral for the built-in ADC (communication_format, channel_format, etc.).
2. What exactly is APB_SARADC_MAX_MEAS_NUM in APB_SARADC_CTRL2_REG? What is the relation to the pattern table? The TRM only describes it as "Max conversion number".

Possibly related:
https://www.esp32.com/viewtopic.php?t=5522
https://github.com/espressif/esp-idf/issues/1911

[szmodz]

A couple of more observations:

1. The selected sampling rate is not respected even in single channel mode. APB_SARADC_MAX_MEAS_NUM seems to affect the sampling rate. The WS clock output is at the expected frequency, but some samples seem to be skipped by the hardware.

Some combinations, i.e.
APB_SARADC_MAX_MEAS_NUM = 2, SampleRate * 3
APB_SARADC_MAX_MEAS_NUM = 3, SampleRate * 2
APB_SARADC_MAX_MEAS_NUM = 5, SampleRate * 3/2

Seem to result in a correct sampling rate.

2. There are bugs in the i2s clock configuration code. Sometimes wrong divisor values get calculated (i.e. in the case of 5000Hz).


So it seems like there is currently no documented way to continuously sample the ADC using I2S, even only a single channel.

What is APB_SARADC_MEAS_NUM_LIMIT? Is it not possible to disable the limit set by APB_SARADC_MAX_MEAS_NUM?

[szmodz]

There's also the undocumented register:

Code: Select all

    union {
        struct {
            volatile uint32_t rstb_wait:    8;
            volatile uint32_t standby_wait: 8;
            volatile uint32_t start_wait:   8;
            volatile uint32_t sample_cycle: 8;            /*sample cycles*/
        };
        volatile uint32_t val;
    }saradc_fsm;

Which also seems to iteract with this.

It seems it's impossible to continuously sample the ADC using I2S, even using only a single channel. The esp-idf example code is broken and the required information is missing.

[detlier]

So I've been having a similar problem, see this forum post and issue #3686. Maybe we can compare notes. I have an example project here that might help for debugging and sharing information.

Regarding the sample rate calculation, note that using the APLL is explicitly (but not super clearly) warned against in the technical reference manual. See issue #3692 (which was invalid but still contains relevant info).

I will look into those registers you mentioned.

[szmodz]

I don't think it's possible to continuously sample the ADC using I2S DMA. There is no working example in the esp-idf and many ADC registers are undocumented.

It's either a hardware problem, or some crucial piece of documentation is missing. Either way, I've given up on using the I2S method.

I've settled for using high-level interrupts and software sampling using the Xtensa timer 2 interrupt (ETS_INTERNAL_TIMER2_INTR_SOURCE). ~100kSPS is possible using this method and it needs some assembly coding.

https://docs.espressif.com/projects/esp ... rupts.html

https://docs.espressif.com/projects/esp ... alloc.html

[Gianluca.Loi]

Hi szmodz,

I'm sampling two different signals using I2S in this moment.
Which kind of problems are you finding during your development?

Gianluca,

[xenpac]

any progress on this??

i am also trying to get 1Msps using i2s.

[Fenhasan]

Hi szmodz,

I'm sampling two different signals using I2S in this moment.
Which kind of problems are you finding during your development?

Gianluca,

Hi Gianluca, sorry for reviving an old post, but I've been trying to read the internal ADC using I2S, and I haven't had much luck. Could you provide some code snippets, to understand how to correctly setup this device? Thanks in advance!