I2C transmission errors. Rounded I2C clock edge from ESP module?

[RMandR]

I have I2C configured for PIN 32 SDL and 33 SCL.

There are external 10K pull-ups resistors, and I've tried a few different boards including connecting DEV-KIT-C to an Adafruit and SparkFun boards with simple copper traces.

Code: Select all

	int i2c_master_port = I2C_NUM;
	i2c_config_t conf;
	conf.mode = I2C_MODE_MASTER;
	conf.sda_io_num = I2C_SDA_IO;
	conf.scl_io_num = I2C_SCL_IO;
	conf.sda_pullup_en = GPIO_PULLUP_DISABLE; //GPIO_PULLUP_ENABLE;
	conf.scl_pullup_en = GPIO_PULLUP_DISABLE; //GPIO_PULLUP_ENABLE;
	conf.master.clk_speed = 100000; //100000; //SHT31_FREQ_HZ;

	ESP_ERROR_CHECK(i2c_param_config(i2c_master_port, &conf));
	ESP_ERROR_CHECK(i2c_driver_install(i2c_master_port, conf.mode, I2C_RX_BUF_DISABLE, I2C_TX_BUF_DISABLE, 0));
	vTaskDelay(100 / portTICK_PERIOD_MS);

Below is what the clock edge looks like. There seems to be some capacitance perhaps slowing the rise edge.

Is there a hardware setting I've missed for this?

Thanks in Advance!

NewFile5.png (47.79 KiB) Viewed 9034 times

[burtrum]

The I2C pins are Open Drain and OD circuits tend to have slow rise time unless you use minimal resistor values.
Rise time is a factor of total distributed capacitance.
Remember the resistor pulls the OD line high. The chip pulls it low.

I find that 10K pull-ups are best used with V = 5V. I use 4.7 K for 3.3V for my I2C.
It’s also a power consumption tradeoff.

I also find capacitance for most prototype setups is higher than desired.
dev boards with internal wire lengths + pluggable breadboard capacitance + long wires can really add up.

I use solderable inexpensive prototype pattern pcbs to make one of boards with the dev module socketed, with short wires.

You might want to run a balanced capacitive pair for longer runs. So each signal drives the same C, per the Philip’s IIC (i2c) spec.
pair 1 3V3 + SDA
pair 2 GND + SCL

I twist the pair a wires with my hand drill. Mark the power/ground wires or use different colors.
Or tie a pair to some weight and spin the weight.

Oh I still have ugly rise times, but within spec.

Burtrum

[bobtidey]

Are you using x10 probes to view these signals? A x1 probe has significant capacitance and could well explain the rise time.

[RMandR]

Are you using x10 probes to view these signals?

Didn't know 10X was better.

I still get the CRC errors on I2C when the probe is not attached. And, I normally see clean clock edges with the same probe and different chip. It can't be probe.

[TomWS1]

I agree with @bobtidey, definitely use a 10X probe while probing clock signals, but also, for I2C, I would not recommend any pullup resistor above 5K.

[RMandR]

Update: I place 2.2K Ohm pull ups which reduces the clock rise time to below 1us (750ns) which is the minimum for 100KHz I2C clock according to the standard and this app note from TI: http://www.ti.com/lit/an/slva689/slva689.pdf

I'm still getting the same rate of CRC errors (~10%) where I wasn't getting any on the Arm Cortex chip I was using prior to esp32 with 10K pull ups.

Also, @bobtidey: turns out I was indeed using the 10X probe and had set the scope to 10X as well and forgotten it was 10X.

So, what now? go to 1K res?

-a

NewFile6.png (42.33 KiB) Viewed 8937 times

[RMandR]

Final Update:

Ok, so this whole did not have anything to do with pull up resistor settings.

The reason I was getting CRC errors was that i2c_master_cmd_begin was returning an error and I was not checking it.

For those who are interested:

i2c_get_data_timing(0, &sample_time, &hold_time); shows that ESP32 samples the SDA line about 2.5us after the rising clock edge. So even 10K resistors should be ok (as noted by others, stronger pull-ups are recommended).