ESP32 Webradio

[BuddyCasino]

Looked at it some more, still don't understand it. Is this a hack to output 32 Bit per channel on an otherwise 24 Bit I2S subsystem?

[Jakobsen]

Hi BuddyCasino

I mite have chance other place ind the i2s driver - I will clean up later tonight and do a simpler hack to the driver layer.

The i2s driver used the sample rate and bits pr sample to setup i2s_bck and i2s_ws clock and ratio.
For 44100 and 32 bits we get a 1/44100 period i2s_ws and a 2.844 MHz i2s_bck. All ok.
The we spec the operation mode TX left and right and for this setup the driver needs to push 8 chars to the DMA buffer pr sample (32bits left and 32 bits right data). The driver is also do all ok here.

My 10 cent is that the hardware i2s module do not play by the rules and only consume 2x16 bits pr sample aka 4 chars per sample from the DMA buffer. Properly also what you saw in the 8 bit case : you put 2x8 bits to the DMA buffer but hardware consumes 2x16 bits.

/Jorgen

[BuddyCasino]

Got it, that would explain the buffer underruns in 8 Bit mode. Maybe someone from Espressif can chime in?

[ESP_Sprite]

Sorry, I can't really help you in the way I'd like... I learned yesterday that some engineers have the 32-bit mode working, but had to patch the I2S hardware driver. I asked them where I can find that patch, but unfortunately they've already gone on holiday. What I can do is give you some information from an internal, as-yet-unverified and unedited document, that may get you going. According to that, you may have problems with I2S_TX_FIFO_MOD, which should be 2 for stereo 32bit-per-sample data; my guess is that the driver leaves it at 0. Maybe you can see if that fixes your problem?

[Jakobsen]

Hi Spirte
Thangs a lot looking into to this. I did poke around with TX_FIFO_MOD in my search to get 32 bits out of you impressive chip. From what I saw it did some Left/Right shit around but no sign of live in the 17-32 bit of audio i2s_data stream. But I will give it a try tonight.

I succeed last night to hook it up to our own 2x70W amplifier - but unfortunate we relay on a low jitter i2s_bck and the result was a solid 16 bit web audio steam - but with a high noise floor due to i2s_bck jitter. Is there a way to reduce that jitter?

Regards Jørgen

[Jakobsen]

Hi Spirit and BuddyCasino
Thanks a lot - Rockon here.



TX_FIFO_MOD = 2 did the trick, rolled back my changes on the i2s driver.
I now have full 32 bits through the DMA/i2s hardware and into my amplifier. Even enabled the stereo mode to the MAD MP3 decoder - and it do not have any problem keeping up the pace.
Buddy: I have still not pulled in you updates - I was to buzzy to get to this point. Still have some hizz due to clock jitter and also consider bringing the MAD decoder back to the full 24 bit resolution. If you want to play with our amp let me know.

/Jørgen

[BuddyCasino]

Sure, just send me a pull request and I'll integrate the changes. Stereo synth might be interesting to lots of folks.

[ESP_Sprite]

I succeed last night to hook it up to our own 2x70W amplifier - but unfortunate we relay on a low jitter i2s_bck and the result was a solid 16 bit web audio steam - but with a high noise floor due to i2s_bck jitter. Is there a way to reduce that jitter?

Do you have any numbers to go with that jitter? Fyi, we have a separate audio PLL in the ESP32, but unfortunately the details of that aren't public yet (as in: I'd love to tell you here, but I don't have any internal docs on it and our HW engineers are on holiday). Maybe enabling that can help; I'll ask around after Chinese new year.

[BuddyCasino]

Just found out that the audio PLL appears in the errata document [0] in section 3.7, for chip revision 0.
Not sure if that affects us in any way.

[0] https://espressif.com/sites/default/fil ... p32_en.pdf

[Jakobsen]

I did try to enable the clka_en bit in the i2s_reg io inteface but there are properly more to setup that baby.

Code: Select all

  union {
        struct {
            uint32_t clkm_div_num: 8;
            uint32_t clkm_div_b:   6;
            uint32_t clkm_div_a:   6;
            uint32_t clk_en:       1;
            uint32_t clka_en:      1;
            uint32_t reserved22:  10;
        };
        uint32_t val;
    } clkm_conf;
 

Thanks