ESP32 Free Heap

[ESP_Sprite]

Fyi, from what I remember the amount of D-port RAM is 328K at maximum; the rest is IRAM, cache etc. We actually feed the free IRAM into the dynamic memory allocator as well; you can allocate it using pvPortMallocCaps(size, MALLOC_CAP_32BIT). (Or at least, you should be able to; something broke, I'm working on a MR to make this work again.)

We indeed will be working on minimizing esp-idf RAM usage at a certain point in time; for now, we think it's more important to get all features in first.

[kolban]

I had failed to notice the following at the start of a boot log:

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I (1080) heap_alloc_caps: Initializing. RAM available for dynamic allocation:
I (1081) heap_alloc_caps: At 3FFC2144 len 0001DEBC (119 KiB): DRAM
I (1083) heap_alloc_caps: At 3FFE8000 len 00018000 (96 KiB): D/IRAM
I (1092) heap_alloc_caps: At 4009C2A0 len 00003D60 (15 KiB): IRAM
I (1100) cpu_start: Pro cpu up.

This seems to say we have a current max of 119 + 96 + 15 = 230K.

Later ... following on from Mr Sprite's comment, I dug to see if I could find out how much IRAM might be available for allocation. On a fresh boot, I ran the following statement:

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LOGD("Free IRAM: %d",  xPortGetFreeHeapSizeTagged(MALLOC_CAP_32BIT));

Result: Free IRAM: 15704

This matches the log statement prior. I am also led to believe that for RAM addressing, we have:

• 256K - 0x3FFB 0000 - 0x3FFF 0000 - Data RAM
• 128K - 0x4008 0000 - 0x400A 0000 - Instruction RAM

But I seem to be missing the last 128K to bring my total up to the 512K of RAM I think the ESP32 should have.

[ESP_Sprite]

In total, there's 516K of memory. Of these:
- 32K is used for flash cache on CPU0
- If enabled, 32K is used for flash cache on CPU1
- 8K+16K are used by the ROM
- If BT is enabled, 64K is used by BT ROM

Fyi, esp-idf/components/esp32/heap_alloc_caps.c gives a good overview; the regions struct array defines what memory is available, the start of heap_alloc_init disables regions that are reserved.

[zizoalbert]

Hello,
I need for your help to understand the memory mapping in esp32.
it serves what this part of memory :
{ (uint8_t *)0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
{ (uint8_t *)0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0

whats does it mean blk 0 ? blk1?

thank you

[ESP_Sprite]

It's a hardware detail; iirc some internal debugging stuff can use one of these. It's not really relevant for software, you can look at these as just two normal memory blocks.

[zizoalbert]

Hello,
Thank you for your help.
After reading a lot of document and looking in the code and on the INTERNET, I came to this conclusion :

RAM (512 KB) = IRAM (128 KB) + DRAM (384 KB)

*****DRAM*********************************************************************************************
---DRAM mapping------- (384 KB)
Bt stack (64K) (0x3FFB0000 - 0x3FFC0000) (can use it if BT is not activated)
Heap (0x3FFC0000- 0x3FFF0000)
MAC dump (0x3FFF0000-0x3FFF8000) (Can't write in it)
Memory trace (0x3FFF8000 + 64K) (Can writ in it if it's not activated)
---------------------------------------------------------------
- If we want know the available DRAM memory we can use this function : esp_get_free_heap_size()
-we can use it if we use : DRAM_ATTR

*** IRAM ************************************************************************************************
---IRAM mapping------ (128 KB)
Flash cache for PRO and APP cpu (0x40070000-0x40080000)
Stack (0x40080000-0x400A0000)
---------------------------------------------
- To know the available IRAM memory we can use this function : xPortGetFreeHeapSizeTagged(MALLOC_CAP_32BIT))
- We can use it if we use : IRAM_ATTR


I want to know if my conclusion is right or it is wrong or it missing some things? Thank you

[ESP_Sprite]

That is almost correct. Asking for the amount of MALLOC_CAP_32BIT will give you back all memory that can handle 32-bit aligned reads; because the DRAM can also do this you will also get this included. Also, part of the DRAM you mentioned actually can also be used as IRAM, if needed.