What would you like to see in The Next Chip?

[routeur01]

Hi,

it would be very interesting to make a lightsleep only for only one core.

[SomeESPDev]

MIPI DSI: If you're in real need of it, the ESP32 can actually fake MIPI compatibility with an external flipflop and some resistors. I have that working now, will publish the project eventually. Agreed that compatibility can be useful; will take a look at it.

Larger flash ROM for data: You are aware that you can add an external SPI flash to the ESP32 and control that with the built-in SPI driver? Alternatively, we have a pretty nice SD-card peripheral and sdriver.

SD-card: We do have SDIO slave support, so in theory you could be able to plug in the ESP32 into your PC already. We don't really have a workflow to go along with it when you want to use that to develop your standalone ESP32 application, however.

I'm interested in how you connected ESP32 to a MIPI DSI device. I did not find any further documentation on this. This would be a huge cost saver, compared to alternatives like the STM32F769 (about $75 for a board) or a Raspberry Pi + HDMI-MIPI-Adapter ($35 + $50).

There are cheap 2K-LCD panels for only 30$ (LS055R1SX03; four data lanes) which can be used as high definition UV-masks for SLA 3D printers (which selectively cure UV-resins) and homemade high quality PCBs (using UV-photoresist). Both require only slow framerates, and on paper the ESP32 should be capable enough (as it can deliver the needed 100MHz). Connecting the LCD directly to a low cost microcontroller offers great potential in these areas.

[ESP_Sprite]

I'm interested in how you connected ESP32 to a MIPI DSI device. I did not find any further documentation on this. This would be a huge cost saver, compared to alternatives like the STM32F769 (about $75 for a board) or a Raspberry Pi + HDMI-MIPI-Adapter ($35 + $50).

See here. Note that I'd classify this as a hack; I have no idea to what extent this is compatible with all MIPI displays.

[skydev]

I have though out a possible use-case for tri or quad core chip:

Extra core could process some signal modulation in real-time (for example 13.56 MHz RFID, but may be more useful with any other generic stuff with much lower frequency then for example 160 MHz) while other cores pipe out / in data and work with it.

It may be problematic to do input on core that it shared with other processess because they will cause modulation data "misses" because of scheduling and switching.

Even using interrupts may fail to process incoming carrier in time.

[ESP_Sprite]

I get your point, but normally you'd use DMA for this. Allow DMA to receive a chunk of data , then use a DMA-complete interrupt to process this. Meanwhile, the DMA receives the next chunk. It doesn't matter if the interrupt has a bit of latency, because the DMA memory provides a 'buffer' against this. Note that you can already do this with the I2S subsystem in the ESP32.

[mikemoy]

What would you like to see in The Next Chip?

The next Chip

[woofy!]

What would you like to see in The Next Chip?

The next Chip

[woofy!]

This is just speculation for the next (or a future) chip, but maybe it will have a change of processor to RISC-V.
The current Xtensa CPU is a Cadence product and both Cadence and Espressif are members of the RISC-V organisation.
https://riscv.org/members-at-a-glance/

[ESP_Sprite]

Hehe, I won't deny we're looking into RiscV as an architecture. As I mentioned before, note that from a business perspective, RiscV is not that much more attractive than Xtensa: you still need to pay someone for an implementation (or invest time to become experts in one of the open-source implementations), and Xtensa is not that expensive to license. Regardless, from a technical perspective, RiscV certainly is interesting, and we do have some ideas that incorporate the ISA.

[arunbm123]

hi

please give us proper documents on debugging with jTag.

it will help us..The Current document I am struggling since 15 days and no one is helping.