Guru Meditation Error: Cache disabled but cached memory region accessed

[chromebin]

Hi, I'm suffering a:

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Guru Meditation Error: Core  0 panic'ed (Cache disabled but cached memory region
 accessed)
Core 0 register dump:
PC      : 0x400f1774  PS      : 0x00060034  A0      : 0x80083c0e  A1      : 0x3f
fb05b0
0x400f1774: gpio_set_level at C:/msys32/home/user/esp/esp-idf/components/driver/
gpio.c:537

A2      : 0x3ffb08f0  A3      : 0x00000008  A4      : 0x00000000  A5      : 0x00
000003
A6      : 0x3ff42000  A7      : 0x700000bb  A8      : 0x800826e6  A9      : 0xd0
000040
A10     : 0x00000010  A11     : 0x00000001  A12     : 0x00000000  A13     : 0x00
000000
A14     : 0x3ff42000  A15     : 0x700000bb  SAR     : 0x0000001c  EXCCAUSE: 0x00
000007
EXCVADDR: 0x00000000  LBEG    : 0x4000c2e0  LEND    : 0x4000c2f6  LCOUNT  : 0xff
ffffff
Core 0 was running in ISR context:
EPC1    : 0x400621b0  EPC2    : 0x00000000  EPC3    : 0x00000000  EPC4    : 0x40
0f1774
0x400f1774: gpio_set_level at C:/msys32/home/user/esp/esp-idf/components/driver/
gpio.c:537


Backtrace: 0x400f1774:0x3ffb05b0 0x40083c0b:0x3ffb05d0 0x40082016:0x3ffb0600 0x4
00621ad:0x00000000
0x400f1774: gpio_set_level at C:/msys32/home/user/esp/esp-idf/components/driver/
gpio.c:537

0x40083c0b: spi_intr at C:/msys32/home/user/esp/esp-idf/components/driver/spi_ma
ster.c:432

0x40082016: _xt_lowint1 at C:/msys32/home/user/esp/esp-idf/components/freertos/x
tensa_vectors.S:1105

Which occurs sometimes on accessing the NVS:

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(nvs_set_blob(kv_store, NVS_NAMESPACE_CFG, pbuf, size) == ESP_OK)

Note the absence of my own code in the trace.

The NVS has long been initialized and the above code is *only* accessed from the thread which triggers a save to the NVS after a request to do so and a timeout. Though I presume the NVS has semaphores to protect against simultaneous access, in my case only one access is possible at a time.

I've read other discussions of "Guru Meditation Error: Cache disabled but cached memory region accessed" but none seems applicable, as I have no ISR in this project (except for ESPNOW callbacks) and the cache was initialized "long ago".

Any idea why this might happen?

The topics closest were:
https://github.com/espressif/esp-idf/issues/1396
https://github.com/espressif/arduino-esp32/issues/855

[WiFive]

What is the code at

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spi_intr at C:/msys32/home/user/esp/esp-idf/components/driver/spi_master.c:432

and what is your esp-idf version?

[ESP_Sprite]

My guess is:
- You are using a SPI peripheral (LCD or something)
- The SPI peripheral is using a pre-transaction callback that sets a GPIO to some level
- You have SPI_MASTER_ISR_IN_IRAM enabled in menuconfig.

If so, the pre-transfer callback will be called, from an interrupt context, even when the cache is disabled. This means anything that is not in IRAM cannot be called from there. The GPIO driver is not in IRAM, hence the crash.

The easiest solution would be to disable SPI_MASTER_ISR_IN_IRAM, this works if you don't mind a slowdown in SPI stuff during flash access. The next easier one is to set the GPIO using direct register access (something like GPIO.w1ts=(1<<gpio_to_make-high)).

To be fair, this is a pretty obscure side effect of SPI_MASTER_ISR_IN_IRAM; we need to make this clearer to users somehow.

[chromebin]

ESP_Sprite, your diagnosis is scaringly spot on. I use SPI to stream data into a shift register, then latch that data in an SPI callback

Now with regard to the remedy.

In sdkconfig I found:

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#
# SPI master configuration
#
CONFIG_SPI_MASTER_IN_IRAM=
CONFIG_SPI_MASTER_ISR_IN_IRAM=y

I suppose the CONFIG_SPI_MASTER_ISR_IN_IRAM is the culprit. But I can't seem to find the menuconfig entry that modifies this setting. I find myself scanning options a lot.

I implemented the preferred remedy:

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//from #include "soc.h"
#define DR_REG_GPIO_BASE            0x3ff44000
//from #include "gpio_reg.h"
#define GPIO_OUT_W1TS_REG           (DR_REG_GPIO_BASE + 0x0008)
#define GPIO_OUT_W1TC_REG          (DR_REG_GPIO_BASE + 0x000c)

...

    // latch the data
    REG_WRITE(GPIO_OUT_W1TS_REG, BIT(GPIO_NUM_16));     // set
    delay_us(2);
    REG_WRITE(GPIO_OUT_W1TC_REG, BIT(GPIO_NUM_16));     // clear

I extracted the #defines from the mentioned #includes, because I have manually configured include paths (I have yet to encounter someone who has seen a properly configured Eclipse workspace). So as usual things didn't work (or maybe it was just the Eclipse side of this mess), even after adding 3 search paths (${IDF_PATH}/components/soc/include/soc, ${IDF_PATH}/components/soc/include, ${IDF_PATH}/components/soc/esp32/include/soc). Madness.

So now the above code runs, I'll report back when the errors reappear. Excellent work ESP_Sprite!

[ESP_Sprite]

That will work. For your not being able to find the menuconfig option problem: you can search in menuconfig using the / key, that will give you something like this:

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Search (SPI_MASTER_IN)
Symbol: SPI_MASTER_IN_IRAM [=n]
Type  : boolean
Prompt: Place transmitting functions of SPI master into IRAM
  Location:
    -> Component config
      -> Driver configurations
(1)     -> SPI configuration
  Defined at /home/jeroen/esp32/esp-idf/components/driver/Kconfig:25
  Selects: SPI_MASTER_ISR_IN_IRAM [=y]        

Note the 'Location:' bits tell you exactly what menus to drill down to.

[anandvilayil]

hi,
i am also getting "Cache disabled but cached memory region accessed" at the time of reading any thing from flash. do any one know why this raised?.

thanks

[ESP_Sprite]

Basically, during flash writes you cannot access the memory that is mapped to flash. In case you have normal (not at the very highest priority) tasks and interrupts that aren't allocated with the flag indicating they live in IRAM, all tasks and interrupts will automatically be disabled during this. If you do have one of those two exceptions, they will keep running; if they access flash anyway, you'll get that exception. Without knowing what code you have, there's not really anything more to say.

[anandvilayil]

actually after migrating to esp-idf 3.2 i felt with this issue only ones in a while. the similar code with esp-idf 3.1 i did't met with this issue. sorry that i can not able to send you the code, that is belongs to my employer. are the coredump file and .elf file useful to find the issue?

[ESP_Sprite]

It would help if you could at least post a backtrace.

[anandvilayil]

hi,
below shows portion of the backtrace log

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[0;32mI (49460) chime-nvs: writing [key7 = 7] to storage nvs[0m
Guru Meditation Error: Core  0 panic'ed (Cache disabled but cached memory region accessed)
Core 0 register dump:
PC      : 0x40086fe4  PS      : 0x00060034  A0      : 0x8008aa84  A1      : 0x3ffbe190  
[0;33m0x40086fe4: btdm_lpcycles_2_us at /home/amruthanand/Desktop/esp32/esp-idf/components/bt/bt.c:1196
[0m
A2      : 0x0000014b  A3      : 0x00000001  A4      : 0x80099ff4  A5      : 0x3ffd4390  
A6      : 0x3ffae270  A7      : 0x0000b440  A8      : 0x3f8046c4  A9      : 0xbad00bad  
A10     : 0x0000000a  A11     : 0x3ffd4370  A12     : 0x80099d9f  A13     : 0x3ffd4360  
A14     : 0x3ffae270  A15     : 0x00013ffc  SAR     : 0x0000001a  EXCCAUSE: 0x00000007  
EXCVADDR: 0x00000000  LBEG    : 0x4009c04d  LEND    : 0x4009c05d  LCOUNT  : 0xfffffffe  
[0;33m0x4009c04d: strlen at /home/jeroen/esp8266/esp32/newlib_xtensa-2.2.0-bin/newlib_xtensa-2.2.0/xtensa-esp32-elf/newlib/libc/machine/xtensa/../../../../.././newlib/libc/machine/xtensa/strlen.S:84
[0m
[0;33m0x4009c05d: strlen at /home/jeroen/esp8266/esp32/newlib_xtensa-2.2.0-bin/newlib_xtensa-2.2.0/xtensa-esp32-elf/newlib/libc/machine/xtensa/../../../../.././newlib/libc/machine/xtensa/strlen.S:96
[0m
Core 0 was running in ISR context:
EPC1    : 0x4000bfe2  EPC2    : 0x00000000  EPC3    : 0x00000000  EPC4    : 0x40086fe4
[0;33m0x40086fe4: btdm_lpcycles_2_us at /home/amruthanand/Desktop/esp32/esp-idf/components/bt/bt.c:1196
[0m

Backtrace: 0x40086fe4:0x3ffbe190 0x4008aa81:0x3ffbe1b0 0x4008b263:0x3ffbe1d0 0x4008afba:0x3ffbe1f0 0x4008b5c3:0x3ffbe210 0x40085155:0x3ffbe230 0x4006222d:0x00000000
[0;33m0x40086fe4: btdm_lpcycles_2_us at /home/amruthanand/Desktop/esp32/esp-idf/components/bt/bt.c:1196
[0m
[0;33m0x4008aa81: r_rwbt_sleep_wakeup at ??:?
[0m
[0;33m0x4008b263: r_rwip_wakeup at ??:?
[0m
[0;33m0x4008afba: r_rwbt_isr at ??:?
[0m
[0;33m0x4008b5c3: r_rwbtdm_isr_wrapper at intc.c:?
[0m
[0;33m0x40085155: _xt_lowint1 at /home/amruthanand/Desktop/esp32/esp-idf/components/freertos/xtensa_vectors.S:1105
[0m

thank you,