ESP32 pulse counter speed (max frequency)

[recently]

Hello,
one of my project-dreams is a GPS‑disciplined oscillator using a si5351 chip. GPS-disciplined means that the output frequency from the oscillator is measured by a frequency counter using the high precise 1Hz output from a GPS-receiver while the microcontroller is doing the correction. The idea is already implemented on an ATmega328 microcontroller by qrp-labs (see circuit diagram, the SI5351-clk2 is connected to the AVR-PD5 for counting). In contrast to this I want to use an esp32, more precisely an esp-wroom-32, an ublox gps-module and a si5321 breakout board.

The question is, is this generally possible regarding the esp32 pulse counter capabilities? The ATmega328 has a pcnt with a max input frequency of 8 MHz and the used oscillator frequency is nearby. In the esp32-wroom-32_datasheet I can only find the information that there is a counter (I searched for 'counter'). In the esp32 pcnt-example only a 1Hz Signal is handled. That is why I suspect that the esp32 possibly cant`t handle 'high' frequencies.

Does anybody knows the max input frequency of the esp32 pulse counter feature ?
Thank you for information

friendly regards

[ESP_Angus]

Hi recently,

With the input filter disabled, the PCNT module should be able to count up to a 40MHz input clock (half the 80MHz APB frequency). I'm not sure why this specification isn't listed in the datasheet or the TRM.

Do I understand that what you need to do is count the number of cycles from the Si5351 clock output that occur within a single 1 second period, as delimited by the GPS PPS signal?

Each PCNT channel can be connected to both a pulse input and a control input. You can configure the control input to read the PPS signal to disable counting when the PPS signal inverts, and you can also enable a GPIO interrupt on the same pin so this triggers a software interrupt (totally independent to the PCNT module). This way, hardware pulse counting should stop immediately when the PPS signal occurs, and you can process the PCNT output (and reconfigure PCNT for the next period) after the associated GPIO interrupt.

Note that because PCNT counters are only 16 bits wide, you'll need to count overflow events via a software interrupt handler when f>65535Hz. This should be OK though, even at 40MHz there is ~1.6ms to handle this interrupt before PCNT overflows a second time.

[recently]

Hi ESP_Angus,

thank you very much, that answers my question.

The SI5351 has 3 independent outputs. One Output is used as tunable oscillator-output up to 160 MHz. The AVR can count with max. 8 MHz. Therefore another output of the SI5351 is used to generate a "slow" 8MHz signal to be counted by the AVR. If there is a measured difference in the 8MHz-counting the AVR does an equal software-correction for both outputs. I don`t know if I can improve precision and accuracy using a 40MHz-counter but it will not be worse

friendly regards
recently