SPI WP signal

[michprev]

Hi,
from ESP32 Technical Reference Manual:

SPI_WP This bit determines the write-protection signal output when SPI is idle. 1: output high; 0: output low. (R/W)

Modifying this bit changes output level of WP pin but it is kept all the time high / low - it does not change during SPI transmission. Tried both with user transmission and flash transmission (flash_rdid) with no success.

Is it a hardware bug?

[michprev]

Even with flash write status register command (flash_wrsr) WP signal does not change

[michprev]

Also hold signal does not seem to work (bits usr_hold_pol, usr_dout_hold, usr_din_hold, usr_dummy_hold, usr_addr_hold, usr_cmd_hold and usr_prep_hold in USER register).

So WP and HOLD signals does not seem to have any function in classic SPI - it should be mentioned in docs.
Both signals are only usable in Quad SPI - it would make more sense to name them IO2 and IO3.