Interrupt Priority Levels: Lower Numbers = Higher Prio or vice versa?

[Bass Mati]

Hi folks,

in the ESP32 Technical Reference Manual p.36, chapter 2.3.2 CPU Interrupt, table 9, is a list of CPU interrupts and their priority level numbers, but I can't find a statement about their precedence. Is level 0 the highest (after NMI), or level 5?

And: Can a higher priority interrupt request interrupt a lower priority interrupt service routine?

Thanks in advance
Bass

[ESP_igrr]

Level 1 is the lowest:
https://docs.espressif.com/projects/esp ... LAG_LEVEL1

Interrupts with higher level can preempt code running at lower interrupt level.

[Bass Mati]

Thanks!
I haven't looked into the SDK yet, but I thing that is certainly a good idea...